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MB2821BB PDF预览

MB2821BB

更新时间: 2024-01-09 23:37:25
品牌 Logo 应用领域
恩智浦 - NXP 触发器
页数 文件大小 规格书
9页 116K
描述
Dual 10-bit D-type flip-flop; positive-edge trigger 3-State

MB2821BB 技术参数

生命周期:Obsolete包装说明:QFP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84其他特性:POWER OFF DISABLE OUTPUTS TO PERMIT LIVE INSERTION; WITH POWER-UP RESET
系列:MBJESD-30 代码:S-PQFP-G52
长度:10 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER位数:10
功能数量:2端口数量:2
端子数量:52最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装形状:SQUARE
封装形式:FLATPACK最大电源电流(ICC):76 mA
传播延迟(tpd):6.7 ns认证状态:Not Qualified
座面最大高度:2.45 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
宽度:10 mm

MB2821BB 数据手册

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Philips Semiconductors Advanced BiCMOS Products  
Product specification  
Dual 10-bit D-type flip-flop;  
positive-edge trigger (3-State)  
MB2821  
the Low-to-High clock transition, is  
transferred to the corresponding flip-flop’s Q  
output.  
FEATURES  
DESCRIPTION  
20-bit positive-edge triggered register  
The MB2821 high-performance BiCMOS  
device combines low static and dynamic  
power dissipation with high speed and high  
output drive.  
Multiple V and GND pins minimize  
CC  
switching noise  
The 3-State output buffers are designed to  
drive heavily loaded 3-State buses, MOS  
memories, or MOS microprocessors.  
Live insertion/extraction permitted  
Power-up reset  
The MB2821 has two 10-bit, edge triggered  
registers, with each register coupled to ten  
3-State output buffers. The two sections of  
each register are controlled independently by  
the clock (nCP) and Output Enable (nOE)  
control gates.  
Power-up 3-State  
The active Low Output Enable (nOE) controls  
all ten 3-State buffers independent of the  
register operation. When nOE is Low, the  
data in the register appears at the outputs.  
When nOE is High, the outputs are in high  
impedance “off” state, which means they will  
neither drive nor load the bus.  
Output capability: +64mA/–32mA  
Latch-up protection exceeds 500mA per  
Jedec JC40.2 Std 17  
ESD protection exceeds 2000V per MIL  
STD 883 Method 3015 and 200V per  
Machine Model  
Each register is fully edge triggered. The  
state of each D input, one set-up time before  
QUICK REFERENCE DATA  
CONDITIONS  
= 25°C; GND = 0V  
SYMBOL  
PARAMETER  
TYPICAL  
UNIT  
T
amb  
t
t
Propagation delay  
nCP to nQx  
PLH  
PHL  
C = 50pF; V = 5V  
4.6  
ns  
L
CC  
C
Input capacitance  
Output capacitance  
Total supply current  
V = 0V or V  
CC  
4
7
pF  
pF  
µA  
IN  
I
C
V
= 0V or V ; 3-State  
O CC  
OUT  
CCZ  
I
Outputs disabled; V = 5.5V  
120  
CC  
ORDERING INFORMATION  
PACKAGES  
TEMPERATURE RANGE  
ORDER CODE  
DRAWING NUMBER  
52-pin plastic Quad Flat Pack  
-40°C to +85°C  
MB2821BB  
1418B  
PIN CONFIGURATION  
LOGIC SYMBOL  
45  
44  
42  
41  
39  
38 37  
36 35  
34  
52 51 50 49 48 47 46 45 44 43 42 41 40  
1
1Q4  
1Q5  
1Q6  
GND  
39 1D4  
38 1D5  
37 1D6  
36 1D7  
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9  
2
3
4
46  
47  
1CP  
1OE  
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9  
1Q7  
188  
1Q9  
2Q0  
5
6
7
8
35 1D8  
34 1D9  
33 2D0  
32 2D1  
MB2821  
52–pin PQFP  
48  
33  
49  
32  
50  
31  
51  
29  
1
2
3
5
6
7
28  
27  
25  
24  
23  
22  
2Q1  
9
31 2D2  
30 GND  
29 2D3  
28 2D4  
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9  
2Q2 10  
2Q3 11  
2Q4 12  
21  
20  
2CP  
2OE  
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9  
2Q5 13  
27 2D5  
14 15 16 17 18 19 20 21 22 23 24 25 26  
8
9
10  
11  
12  
13  
15  
16  
18  
19  
1
August 24, 1993  
853-1670 10620  

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