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MAX9867ETJ+TG3U PDF预览

MAX9867ETJ+TG3U

更新时间: 2024-01-06 17:15:36
品牌 Logo 应用领域
美信 - MAXIM PC电信电信集成电路
页数 文件大小 规格书
55页 974K
描述
IC STEREO AUD CODEC LP 32TQFN

MAX9867ETJ+TG3U 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:,
Reach Compliance Code:compliantFactory Lead Time:15 weeks
风险等级:5.75峰值回流温度(摄氏度):NOT SPECIFIED
电信集成电路类型:PCM CODEC处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

MAX9867ETJ+TG3U 数据手册

 浏览型号MAX9867ETJ+TG3U的Datasheet PDF文件第7页浏览型号MAX9867ETJ+TG3U的Datasheet PDF文件第8页浏览型号MAX9867ETJ+TG3U的Datasheet PDF文件第9页浏览型号MAX9867ETJ+TG3U的Datasheet PDF文件第11页浏览型号MAX9867ETJ+TG3U的Datasheet PDF文件第12页浏览型号MAX9867ETJ+TG3U的Datasheet PDF文件第13页 
Ultra-Low Power Stereo Audio Codec  
ELECTRICAL CHARACTERISTICS (continued)  
(V  
= V  
REF  
= V  
= 2.2µF, C  
= V  
MICBIAS  
= +1.8V, R = , headphone load (R ) connected between _OUTP and _OUTN in differential  
AVDD  
PVDD  
DVDD  
DVDDIO  
= C  
L
L
mode, C  
= C  
= 1µF, AV  
= +20dB, AV  
= 0dB, AV  
= 0dB, AV  
= +20dB, AV  
=
PREG  
REG  
PRE  
PGAM  
DAC  
LINE  
VOL  
0dB, MCLK = 13MHz, T = T  
to T  
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)  
MAX A  
A
MIN  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
DIGITAL SIDETONE  
Differential output mode,  
DVST = 0x1F to 0x01  
Sidetone Gain Adjust Range  
Voice Path Phase Delay  
AV  
P
-60  
0
dB  
ms  
STGA  
MAX9867  
MIC input to headphone output, f = 1kHz,  
HP filter disabled, f = 8kHz  
S
2.2  
DLY  
INPUT CLOCK CHARACTERISTICS  
MCLK Input Frequency  
f
For any LRCLK sample rate  
Prescaler = /1 mode  
/2 or /4 modes  
10  
40  
30  
60  
60  
70  
MHz  
%
MCLK  
MCLK Input Duty Cycle  
Maximum allowable RMS for performance  
limits  
Maximum MCLK Input Jitter  
LRCLK Sample Rate Range  
100  
ps  
RMS  
8
48  
7
kHz  
Rapid lock mode  
2
Any allowable LRCLK  
LRCLK PLL Lock Time  
and PCLK rate, slave  
mode  
ms  
Nonrapid lock  
mode  
12  
25  
Allowable LRCLK period change from  
nominal for slave PLL mode at any  
allowable LRCLK and PCLK rates  
LRCLK Acceptable Jitter for  
Maintaining PLL Lock  
100  
ns  
%
FREQ = 0x8 through 0xF  
0
0
0
0
LRCLK Average Frequency Error  
(Master and Slave Modes)  
(Note 9)  
PCLK = 192xf , 256xf , 384xf , 512xf ,  
S
S
S
S
768xf , and 1024xf  
S
S
All other modes  
-0.025  
+0.025  
DIGITAL INPUT (MCLK)  
Input High Voltage  
V
1.2  
V
V
IH  
Input Low Voltage  
V
0.6  
1
IL  
Input Leakage Current  
Input Capacitance  
I
, I  
IH IL  
T
A
= +25°C  
µA  
pF  
10  
DIGITAL INPUTS (SDIN, BCLK, LRCLK)  
0.7 x  
DVDDIO  
Input High Voltage  
Input Low Voltage  
V
V
V
IH  
0.3 x  
DVDDIO  
V
IL  
Input Hysteresis  
200  
10  
mV  
µA  
pF  
Input Leakage Current  
Input Capacitance  
I
, I  
IH IL  
T
A
= +25°C  
1
10 ______________________________________________________________________________________  

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