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MAX97002EWP+T PDF预览

MAX97002EWP+T

更新时间: 2024-02-14 09:30:41
品牌 Logo 应用领域
美信 - MAXIM 放大器
页数 文件大小 规格书
36页 3201K
描述
Audio Amplifier, 2 Func, PBGA20,

MAX97002EWP+T 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:FBGA, BGA20,4X5,20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.33.00.01Factory Lead Time:1 week
风险等级:5.79商用集成电路类型:AUDIO AMPLIFIER
JESD-30 代码:R-PBGA-B20JESD-609代码:e1
湿度敏感等级:1功能数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:FBGA封装等效代码:BGA20,4X5,20
封装形状:RECTANGULAR封装形式:GRID ARRAY, FINE PITCH
电源:1.8,3.7 V认证状态:Not Qualified
子类别:Audio/Video Amplifiers最大压摆率:2.7 mA
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.5 mm端子位置:BOTTOM
Base Number Matches:1

MAX97002EWP+T 数据手册

 浏览型号MAX97002EWP+T的Datasheet PDF文件第28页浏览型号MAX97002EWP+T的Datasheet PDF文件第29页浏览型号MAX97002EWP+T的Datasheet PDF文件第30页浏览型号MAX97002EWP+T的Datasheet PDF文件第32页浏览型号MAX97002EWP+T的Datasheet PDF文件第33页浏览型号MAX97002EWP+T的Datasheet PDF文件第34页 
Audio Subsystem with Mono Class D  
Speaker and Class H Headphone Amplifiers  
Early STOP Conditions  
The MAX97002 recognizes a STOP (P) condition at any  
point during data transmission except if the STOP condi-  
tion occurs in the same high pulse as a START (S) condi-  
tion. For proper operation, do not send a STOP condition  
during the same SCL high pulse as the START condition.  
sent when the master reads the final byte of data from  
the MAX97002, followed by a STOP condition.  
Write Data Format  
A write to the MAX97002 includes transmission of a  
START condition, the slave address with the R/W bit set  
to 0, one byte of data to configure the internal register  
address pointer, one or more bytes of data, and a STOP  
condition. Figure 10 illustrates the proper frame format  
for writing one byte of data to the MAX97002. Figure 11  
illustrates the frame format for writing n-bytes of data to  
the MAX97002.  
Slave Address  
The slave address is defined as the seven most sig-  
nificant bits (MSBs) followed by the read/write bit. For  
the MAX97002 the 7 MSBs are 1001101. Setting the  
read/write bit to 1 (slave address = 0x9B) configures the  
MAX97002 for read mode. Setting the read/write bit to 0  
(slave address = 0x9A) configures the MAX97002 for write  
mode. The address is the first byte of information sent to  
the MAX97002 after the START condition.  
The slave address with the R/W bit set to 0 indicates that  
the master intends to write data to the MAX97002. The  
MAX97002 acknowledges receipt of the address byte  
during the master-generated 9th SCL pulse.  
Acknowledge  
The acknowledge bit (ACK) is a clocked 9th bit that  
the MAX97002 uses to handshake receipt each byte  
of data when in write mode (Figure 9). The MAX97002  
pulls down SDA during the entire master-generated 9th  
clock pulse if the previous byte is successfully received.  
Monitoring ACK allows for detection of unsuccessful  
data transfers. An unsuccessful data transfer occurs  
if a receiving device is busy or if a system fault has  
occurred. In the event of an unsuccessful data transfer,  
the bus master retries communication. The master pulls  
down SDA during the 9th clock cycle to acknowledge  
receipt of data when the MAX97002 is in read mode. An  
acknowledge is sent by the master after each read byte  
to allow data transfer to continue. A not-acknowledge is  
The second byte transmitted from the master configures  
the MAX97002’s internal register address pointer. The  
pointer tells the MAX97002 where to write the next byte  
of data. An acknowledge pulse is sent by the MAX97002  
upon receipt of the address pointer data.  
The third byte sent to the MAX97002 contains the  
data that is written to the chosen register. An acknowl-  
edge pulse from the MAX97002 signals receipt of the  
data byte. The address pointer autoincrements to the  
next register address after each received data byte.  
This autoincrement feature allows a master to write to  
sequential registers within one continuous frame. The  
master signals the end of transmission by issuing a  
STOP condition. Register addresses greater than 0x09  
are reserved. Do not write to these addresses.  
CLOCK PULSE FOR  
ACKNOWLEDGMENT  
START  
CONDITION  
SCL  
1
28  
9
NOT ACKNOWLEDGE  
SDA  
ACKNOWLEDGE  
Figure 9. Acknowledge  
31  

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