Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
Charge-Pump Control
Table 7. Charge-Pump Control Register
REGISTER
BIT
NAME
DESCRIPTION
Charge-Pump Output Select. Works with the FIXED to set Q1.8V or Q0.9V outputs on
HPVDD and HPVSS. Ignored when FIXED = 0.
0 = Q1.8V on HPVDD/HPVSS
1
CPSEL
1 = Q0.9V on HPVDD/HPVSS
0x09
Class H Mode. When enabled, this bit forces the charge pump to generate static power
rails for HPVDD and HPVSS, instead of dynamically adjusting them based on output
0
FIXED
signal level.
0 = Class H mode
1 = Fixed-supply mode
I2C Serial Interface
S
Sr
P
The MAX97000 features an I2C/SMBusK-compatible,
2-wire serial interface consisting of a serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL
facilitate communication between the MAX97000 and the
master at clock rates up to 400kHz. Figure 1 shows the
2-wire interface timing diagram. The master generates
SCL and initiates data transfer on the bus. The master
device writes data to the MAX97000 by transmitting the
proper slave address followed by the register address
and then the data word. Each transmit sequence is
framed by a START (S) or REPEATED START (Sr) condi-
tion and a STOP (P) condition. Each word transmitted
to the MAX97000 is 8 bits long and is followed by an
acknowledge clock pulse. A master reading data from
the MAX97000 transmits the proper slave address fol-
lowed by a series of nine SCL pulses. The MAX97000
transmits data on SDA in sync with the master-generated
SCL pulses. The master acknowledges receipt of each
byte of data. Each read sequence is framed by a START
or REPEATED START condition, a not acknowledge, and
a STOP condition. SDA operates as both an input and an
open-drain output. A pullup resistor, typically greater than
500I, is required on SDA. SCL operates only as an input.
A pullup resistor, typically greater than 500I, is required
on SCL if there are multiple masters on the bus, or if
the single master has an open-drain SCL output. Series
resistors in line with SDA and SCL are optional. Series
resistors protect the digital inputs of the MAX97000 from
high-voltage spikes on the bus lines, and minimize cross-
talk and undershoot of the bus signals.
SCL
SDA
Figure 8. START, STOP, and REPEATED START Conditions
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START con-
dition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high (Figure 8). A START
condition from the master signals the beginning of a
transmission to the MAX97000. The master terminates
transmission and frees the bus by issuing a STOP con-
dition. The bus remains active if a REPEATED START
condition is generated instead of a STOP condition.
Early STOP Conditions
The MAX97000 recognizes a STOP condition at any point
during data transmission except if the STOP condition
occurs in the same high pulse as a START condition. For
proper operation, do not send a STOP condition during
the same SCL high pulse as the START condition.
Slave Address
The slave address is defined as the seven most sig-
nificant bits (MSBs) followed by the read/write bit. For the
MAX97000 the seven most significant bits are 1001101.
Setting the read/write bit to 1 (slave address = 0x9B) con-
figures the MAX97000 for read mode. Setting the read/write
bit to 0 (slave address = 0x9A) configures the MAX97000
for write mode. The address is the first byte of information
sent to the MAX97000 after the START condition.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period of
the SCL pulse. Changes in SDA while SCL is high are con-
trol signals (see the START and STOP Conditions section).
SMBus is a trademark of Intel Corp.
28
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