MAX96705A
16-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Absolute Maximum Ratings
AVDD to EP* ........................................................-0.5V to +1.9V
DVDD to EP*........................................................-0.5V to +1.9V
IOVDD to EP*.......................................................-0.5V to +3.9V
OUT+, OUT- to EP*..............................................-0.5V to +1.9V
All Other Pins to EP*............................-0.5V to (IOVDD + 0.5V)
OUT+, OUT- Short Circuit to Ground or Supply........Continuous
Continuous Power Dissipation, T = +70°C
A
TQFN (derate 34.5 mW/°C above +70°C) .............2758.6mW
Operating Temperature Range..........................-40°C to +115°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -40°C to +150°C
Soldering Temperature (reflow).......................................+260°C
*EP connected to IC ground.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
32-Pin TQFN-EP
Package Code
T3255+8
21-0140
90-0013
Outline Number
Land Pattern Number
Single-Layer Board:
Junction-to-Ambient Thermal Resistance (θ
)
)
47
JA
Junction-to-Case Thermal Resistance (θ
)
1.7
JC
Four-Layer Board:
Junction-to-Ambient Thermal Resistance (θ
Junction-to-Case Thermal Resistance (θ
29
JA
)
1.7
JC
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
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