I2C Port Expander with Eight Push-Pull Outputs
Table 3. MAX7320 Address Map
PIN
DEVICE ADDRESS
OUTPUTS POWER-UP DEFAULT
CONNECTION
AD2
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
GND
GND
GND
GND
V+
AD0
GND
V+
A6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
O7
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
O6
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
O5
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
O4
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
O3
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
O2
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
O1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
O0
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
SCL
SDA
GND
V+
SCL
SDA
GND
V+
SCL
SDA
GND
V+
V+
V+
SCL
SDA
V+
addresses (101xxxx) than the MAX7319, MAX7321,
MAX7322, and MAX7323 (110xxxx).
The RST input clears the serial interface in case of a
hung bus, ter5inating any serial transaction to or fro5
the MAX7320.
The MAX7320 slave address is deter5ined on each I2C
trans5ission, regardless of whether the trans5ission is
actually addressing the MAX7320. The MAX7320 distin-
guishes whether address inputs AD0 and AD2 are con-
nected to SDA or SCL instead of fixed logic levels V+
or GND during this trans5ission. This 5eans that the
MAX7320 slave address can be configured dyna5ical-
ly in the application without cycling the device supply.
When the MAX7320 is read through the serial interface,
the actual logic states at the ports are read back.
Output port power-up logic states are selected by the
address select inputs AD0 and AD2. Ports default to
logic-high or logic-low on power-up in groups of four
(see Table 3).
RST Input
On initial power-up, the MAX7320 cannot decode the
address inputs AD0 and AD2 fully until the first I2C
trans5ission. AD0 and AD2 initially appear to be con-
nected to V+ or GND. This is i5portant because the
address selection deter5ines the power-up logic levels
of the output ports. However, at power-up, the I2C SDA
and SCL bus interface lines are high i5pedance at the
pins of every device (5aster or slave) connected to the
bus, including the MAX7320. This is guaranteed as part
of the I2C specification. Therefore, address inputs AD0
and AD2 that are connected to SDA or SCL nor5ally
appear at power-up to be connected to V+. The power-
up output state selection logic uses AD0 to select the
power-up state for ports O3–O0, and uses AD2 to
select the power-up state for ports O7–O4. The rule is
that a logic-high, SDA, or SCL connection selects a
2
The RST input voids any I C transaction involving the
2
MAX7320 and forces the MAX7320 into the I C STOP
condition. A reset does not change the contents of the
output register. RST is overvoltage tolerant to +ꢀ.ꢀV.
Standby Mode
When the serial interface is idle, the MAX7320 auto5at-
ically enters standby 5ode, drawing 5ini5al supply
current.
Slave Address and Power-Up
Default Logic States
Address inputs AD0 and AD2 deter5ine the MAX7320
slave address and set the power-up output logic states.
Power-up logic states are set in groups of four (see
Table 3). The MAX7320 uses a different range of slave
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