10-Port I/O Expander with LED Intensity
Control and Interrupt
The MAX7316 SDA line operates as both an input and
Serial Interface
an open-drain output. A pullup resistor, typically 4.7k ,
is required on SDA. The MAX7316 SCL line operates
only as an input. A pullup resistor, typically 4.7k , is
required on SCL if there are multiple masters on the 2-
wire interface, or if the master in a single-master system
has an open-drain SCL output.
Serial Addressing
The MAX7316 operates as a slave that sends and
receives data through an I2C-compatible 2-wire inter-
face. The interface uses a serial data line (SDA) and a
serial clock line (SCL) to achieve bidirectional commu-
nication between master(s) and slave(s). A master (typ-
ically a microcontroller) initiates all data transfers to and
from the MAX7316 and generates the SCL clock that
synchronizes the data transfer (Figure 2).
Each transmission consists of a START condition
(Figure 3) sent by a master, followed by the MAX7316
7-bit slave address plus R/W bit, a register address
byte, one or more data bytes, and finally a STOP condi-
tion (Figure 3).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
SDA
SCL
S
P
START
STOP
CONDITION
CONDITION
Figure 3. Start and Stop Conditions
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
SDA
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data
(Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse so the SDA line is stable low
during the high period of the clock pulse. When the
master is transmitting to the MAX7316, the device gen-
erates the acknowledge bit because the MAX7316 is
the recipient. When the MAX7316 is transmitting to the
master, the master generates the acknowledge bit
because the master is the recipient.
SCL
DATA LINE STABLE; CHANGE OF DATA
DATA VALID
ALLOWED
Figure 4. Bit Transfer
CLOCK PULSE
START
CONDITION
FOR ACKNOWLEDGE
SCL
1
2
8
9
SDA BY
TRANSMITTER
Slave Address
The MAX7316 has a 7-bit long slave address (Figure 6).
The eighth bit following the 7-bit slave address is the
R/W bit. The R/W bit is low for a write command, high
for a read command.
SDA BY
RECEIVER
S
Figure 5. Acknowledge
SDA
SCL
A6
1
0
0
A2
0
0
R/W
ACK
LSB
MSB
Figure 6. Slave Address
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