2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt and Hot-Insertion Protection
DC ELECTRICAL CHARACTERISTICS (continued)
+
+
(V = 2V to 5.5V, T = -40°C to +125°C, unless otherwise noted. Typical values are at V = 3.3V, T = +25°C.) (Note 1)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
-1
TYP
MAX
UNITS
µA
Leakage Current
+1
Input Capacitance
INT
4
pF
Low-Level Output Current
I
V
= 0.4V
OL
6
mA
OL
AC ELECTRICAL CHARACTERISTICS
+
(V = 2V to 5.5V, T = -40°C to +125°C, unless otherwise noted.) (Note 1)
A
PARAMETER
SCL Clock Frequency
Bus Timeout
SYMBOL
CONDITIONS
MIN
TYP
MAX
400
61
UNITS
kHz
f
(Note 2)
SCL
TIMEOUT
t
29
ms
Bus Free Time Between STOP
and START Conditions
t
Figure 2
Figure 2
1.3
µs
µs
µs
BUF
Hold Time (Repeated) START
Condition
t
0.6
HD,STA
Repeated START Condition
Setup Time
t
Figure 2
Figure 2
0.6
0.6
SU,STA
STOP Condition Setup Time
Data Hold Time
t
µs
µs
ns
µs
µs
SU,STO
t
Figure 2 (Note 3)
Figure 2
0.9
HD,DAT
Data Setup Time
t
100
1.3
0.7
SU,DAT
SCL Low Period
t
Figure 2
LOW
SCL High Period
t
Figure 2
HIGH
V+ < 3.3V
500
250
SDA Fall Time
t
Figure 2 (Notes 4, 5)
(Note 6)
ns
ns
F
V+ ≥ 3.3V
Pulse Width of Spike Suppressed
PORT TIMING
t
t
50
SP
PV
Output Data Valid
Figure 7
3
µs
µs
µs
Input Data Setup Time
Input Data Hold Time
INTERRUPT TIMING
Interrupt Valid
27
0
t
Figure 9
Figure 9
30.5
2
µs
µs
IV
Interrupt Reset
t
IR
Note 1: All parameters are 100% production tested at T = +25°C. Specifications over temperature are guaranteed by design.
A
Note 2: Minimum SCL clock frequency is limited by the MAX7311 bus timeout feature, which resets the serial bus interface if either
SDA or SCL is held low for a minimum of 25ms. Disable bus timeout feature for DC operation.
Note 3: A master device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V of the SCL
IL
signal) in order to bridge the undefined region SCL’s falling edge.
Note 4: C = total capacitance of one bus line in pF.
B
Note 5: The maximum t for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage t is
F
F
specified at 250ns. This allows series protection resistors to be connected between the SDA and SCL pins and the
SDA/SCL bus lines without exceeding the maximum specified t .
F
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
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3