MAX7310AUE-T

更新时间： 2024-01-22 03:44:30

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美信 - MAXIM		/
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数据手册

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MAX7310AUE-T 数据手册

2-Wire-Interfaced 8-Bit I/O Port Expander

with Reset

DC ELECTRICAL CHARACTERISTICS (continued)

(V+ = 2.3V to 5.5V, GND = 0, RESET = V+, T = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = 3.3V, T = +25°C.)

(Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

µA

Leakage Current

-1

Input Capacitance

AC ELECTRICAL CHARACTERISTICS

(V+ = 2.3V to 5.5V, GND = 0, RESET = V+, T = -40°C to +125°C, unless otherwise noted.) (Note 1)

PARAMETER

SCL Clock Frequency

BUS Timeout

SYMBOL

CONDITIONS

MIN

TYP

MAX

400

UNITS

kHz

(Note 2)

SCL

TIMEOUT

Bus Free Time Between STOP

and START Condition

Figure 2

1.3

µs

BUF

Hold Time (Repeated) START

Condition

0.6

HD, STA

Repeated START Condition Setup

Time

Figure 2

0.6

SU, STA

STOP Condition Setup Time

Data Hold Time

µs

SU, STO

Figure 2 (Note 3)

Figure 2

0.9

HD, DAT

Data Setup Time

0.1

1.3

0.7

SU, DAT

SCL Low Period

Figure 2

LOW

SCL High Period

Figure 2

HIGH

SCL/SDA Fall Time (Transmitting)

Pulse Width of Spike Supressed

PORT TIMING

Figure 2 (Note 4)

(Note 5)

250

Output Data Valid

Figure 9

µs

Input Data Setup Time

Input Data Hold Time

RESET

Figure 10

Reset Pulse Width

100

Note 1: All parameters are 100% production tested at T = +25°C. Specifications over temperature are guaranteed by design.

Note 2: Minimum SCL clock frequency is limited by the MAX7310 bus timeout feature, which resets the serial bus interface if either

SDA or SCL is held low for a 30ms minimum.

Note 3: A master device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V of the SCL signal) in

order to bridge the undefined region of SCL’s falling edge.

Note 4: t measured between 90% to 10% of V+.

Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.

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