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MAX6869UK36D5L

更新时间: 2023-08-15 00:00:00
品牌 Logo 应用领域
美信 - MAXIM 信息通信管理光电二极管
页数 文件大小 规格书
17页 489K
描述
Power Supply Management Circuit, Fixed, 1 Channel, BICMOS, PDSO5, MO-178AA, SOT-23, 5 PIN

MAX6869UK36D5L 数据手册

 浏览型号MAX6869UK36D5L的Datasheet PDF文件第8页浏览型号MAX6869UK36D5L的Datasheet PDF文件第9页浏览型号MAX6869UK36D5L的Datasheet PDF文件第10页浏览型号MAX6869UK36D5L的Datasheet PDF文件第12页浏览型号MAX6869UK36D5L的Datasheet PDF文件第13页浏览型号MAX6869UK36D5L的Datasheet PDF文件第14页 
Nanopower µP Supervisory Circuits with  
Manual Reset and Watchdog Timer  
V
CC  
t
t
RP  
t
WD  
WDI  
WDI  
OV  
V
CC  
RESET*  
OV  
*RESET IS THE INVERSE OF RESET.  
Figure 3. Detailed Watchdog Input Timing Relationship  
Watchdog Input  
Detailed Description  
The MAX6864–MAX6869’s watchdog timer circuitry  
monitors the µP’s activity. If the µP does not toggle  
(low-to-high or high-to-low) the watchdog input (WDI)  
RESET/RESET Output  
A µP’s reset input starts the µP in a known state. The  
MAX6854/MAX6855/MAX6856/MAX6858/MAX6860–  
MAX6869 µP supervisory circuits assert a reset to prevent  
code-execution errors during power-up, power-down, and  
brownout conditions. The MAX6854/MAX6855/MAX6856/  
MAX6858/MAX6860–MAX6869 reset output is guaranteed  
within the watchdog timeout period (t  
), reset asserts  
WDI  
for the reset timeout period (t ). The internal timer is  
RP  
cleared when reset asserts, when manual reset is  
asserted, or by a rising or falling edge on WDI. The  
watchdog input detects pulses as short as 150ns.  
While reset is asserted the watchdog timer does not  
count. As soon as reset deasserts, the watchdog timer  
resumes counting (Figure 3).  
to be valid for V down to 1.1V.  
CC  
Whenever V  
falls below the reset threshold, the reset  
output asserts low for RESET and high for RESET.  
Once V exceeds the reset threshold, an internal  
timer keeps the reset output asserted for the specified  
reset timeout period, then after this interval the reset  
output deasserts (see Figure 2).  
CC  
CC  
Applications Information  
Selecting the Reset Timeout Period  
The reset timeout period for the MAX6854/MAX6855/  
MAX6856/MAX6858/MAX6860/MAX6864–MAX6869 is  
fixed (see Table 4). The MAX6861/MAX6862/MAX6863  
feature a reset timeout select input, CT. Connect CT  
according to Table 1 to select between the available  
10ms and 150ms (min) reset timeout periods. The time-  
out period can be changed while a reset timeout period  
is in progress, but will not update until the reset timeout  
period has expired.  
Manual Reset Input  
Many µP-based products require manual reset capabil-  
ity, allowing the operator, a test technician, or external  
logic circuitry to initiate a reset. The MAX6854/  
MAX6855/MAX6856/MAX6861–MAX6869 feature an  
MR input. A logic low on MR asserts a reset. Reset  
remains asserted while MR is low and for the timeout  
period, t , after MR returns high. The devices provide  
RP  
an internal 10kpullup from MR to V . Leave MR  
CC  
unconnected or connect to V  
if unused. MR can be  
CC  
Table 1. MAX6861/MAX6862/MAX6863  
Reset Timeout Period Selection  
driven with CMOS logic levels or with open-drain/col-  
lector outputs. Connect a normally open momentary  
switch from MR to GND to implement a manual reset  
function; external debounce circuitry is not required. If  
MR is driven by long cables or the device is used in a  
noisy environment, connect a 0.1µF capacitor from MR  
to GND to provide additional noise immunity.  
CT CONNECTION  
LOW  
MIN  
10  
TYP  
15  
MAX  
25  
UNITS  
ms  
HIGH  
150  
225  
300  
______________________________________________________________________________________ 11  

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