Dual Ultra-Low-Voltage SOT23 µP Supervisors
with Manual Reset and Watchdog Timer
V
CC
t
V
CC
V
CC
RST
MAX6828
MAX6831
RESET*
WDI
RESET
RESET
µP
t
RP
t
t
RP
WD
RESET
GENERATOR
GND
GND
*RESET IS THE INVERSE OF RESET.
Figure 6. Interfacing Open-Drain RESET to µPs with
Bidirectional Reset I/O
Figure 4. Watchdog Timing Relationship
the maximum allowable leakage current is 10µA and the
maximum allowable load capacitance is 200pF.
V
MONITOR
MAX6826
MAX6827
MAX6828
Adjustable Reset Thresholds
The MAX6826/MAX6827/MAX6828 provide a user
adjustable input to monitor a second voltage. The
threshold voltage at RSTIN is typically 0.63V. To moni-
tor a voltage higher than 0.63V, connect a resistor-
divider to the circuit as shown in Figure 5. The
R1
R2
RSTIN
threshold at V
is:
MONITOR
V
≥ V
RSTIN
CC
R1 + R2
V
= 0.63V
MONITOR_TRIP
R2
Figure 5. Monitoring a Voltage
outputs. Connect a normally open momentary switch
from MR to GND to create a manual-reset function;
external debounce circuitry is not required. If MR is dri-
ven from long cables or the device is used in a noisy
environment, connect a 0.1µF capacitor from MR to
GND to provide additional noise immunity.
Note that RSTIN is powered by V , and its voltage
CC
.
must therefore remain lower than V
CC
Applications Information
Watchdog Input Current
The WDI inputs are internally driven through a buffer
and series resistor from the watchdog timer (Figure 1).
When WDI is left unconnected, the watchdog timer is
serviced within the watchdog timeout period by a low-
high-low pulse from the counter chain. For minimum
watchdog input current (minimum overall power con-
sumption), leave WDI low for the majority of the watch-
dog timeout period, pulsing it low-high-low once within
the first 7/8 of the watchdog timeout period to reset the
watchdog timer. If WDI is externally driven high for the
majority of the timeout period, up to 160µA can flow into
WDI.
Watchdog Input
The watchdog circuit monitors the µP’s activity. If the
µP does not toggle (low to high or high to low) the
watchdog input (WDI) within the watchdog timeout peri-
od (1.6s nominal), reset asserts for the reset timeout
period. The internal 1.6s timer can be cleared by either
a reset pulse or by toggling WDI. The WDI can detect
pulses as short as 50ns. While reset is asserted, the
timer remains cleared and does not count. As soon as
reset is released, the timer starts counting (Figure 4).
Disable the watchdog function by leaving WDI uncon-
nected or by three-stating the driver connected to WDI.
The watchdog input is internally driven low during the
first 7/8 of the watchdog timeout period and high for the
last 1/8 of the watchdog timeout period. When WDI is left
unconnected, this internal driver clears the 1.6s timer
every 1.4s. When WDI is three-stated or unconnected,
Interfacing to µPs
with Bidirectional Reset Pins
Since the RESET output on the MAX6828/MAX6831
is open drain, these devices interface easily with µPs
that have bidirectional reset pins, such as the Motorola
68HC11. Connecting the µP supervisor’s RESET output
_______________________________________________________________________________________
9