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MAX6734AKAMRD6+T

更新时间： 2024-02-11 21:38:02
品牌 Logo 应用领域
美信 - MAXIM 输入元件信息通信管理光电二极管
页数 文件大小 规格书
16页 460K
描述
Power Supply Management Circuit, Adjustable, 1 Channel, BICMOS, PDSO8, LEAD FREE, MO-178BA, SOT-23, 8 PIN

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中文翻译

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MAX6734AKAMRD6+T 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：LSSOP,针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.09
其他特性：RESET THRESHOLD VOLTAGES ARE 4.375V AND 2.625V; MANUAL RESET INPUT可调阈值：YES
模拟集成电路 - 其他类型：POWER SUPPLY MANAGEMENT CIRCUITJESD-30 代码：R-PDSO-G8
JESD-609代码：e3长度：2.9 mm
信道数量：1功能数量：1
端子数量：8最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：LSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.45 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：0.8 V
表面贴装：YES技术：BICMOS
温度等级：AUTOMOTIVE端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：1.6 mmBase Number Matches：1

MAX6734AKAMRD6+T 数据手册

 浏览型号MAX6734AKAMRD6+T的Datasheet PDF文件第4页浏览型号MAX6734AKAMRD6+T的Datasheet PDF文件第5页浏览型号MAX6734AKAMRD6+T的Datasheet PDF文件第6页浏览型号MAX6734AKAMRD6+T的Datasheet PDF文件第8页浏览型号MAX6734AKAMRD6+T的Datasheet PDF文件第9页浏览型号MAX6734AKAMRD6+T的Datasheet PDF文件第10页 
Single-/Dual-/Triple-Voltage µP Supervisory  
Circuits with Independent Watchdog Output  
Pin Description  
PIN  
NAME  
FUNCTION  
MAX6730A MAX6732A MAX6734A  
MAX6731A MAX6733A MAX6735A  
Active-Low Reset Output. The MAX6730A/MAX6732A/MAX6734A provide an  
open-drain output. The MAX6731A/MAX6733A/MAX6735A provide a push-pull  
1
2
1
2
1
2
RST  
output. RST asserts low when any of the following conditions occur: V 1 or  
CC  
V
2 drops below its preset threshold, RSTIN drops below its reset threshold,  
CC  
or MR is driven low. Open-drain versions require an external pullup resistor.  
GND Ground  
Active-Low Watchdog Output. The MAX6730A/MAX6732A/MAX6734A provide  
an open-drain WDO output. The MAX6731A/MAX6733A/MAX6735A provide a  
push-pull WDO output. WDO asserts low when no low-to-high or high-to-low  
transition occurs on WDI within the watchdog timeout period (t ) or if an  
WD  
3
3
4
WDO  
undervoltage-lockout condition exists for V 1, V 2, or RSTIN. WDO  
CC  
CC  
deasserts without a timeout period when V 1, V 2, and RSTIN exceed their  
CC  
CC  
reset thresholds, or when the manual reset input is deasserted. Open-drain  
versions require an external pullup resistor.  
Active-Low Manual Reset Input. Drive MR low to force a reset. RST remains  
asserted as long as MR is low and for the reset timeout period after MR releases  
4
5
—
5
5
3
MR  
high. MR has a 50kΩ pullup resistor to V 1; leave MR open or connect to  
CC  
V
1 if unused.  
CC  
Watchdog Input. If WDI remains high or low for longer than the watchdog  
timeout period, the internal watchdog timer expires and the watchdog output  
asserts low. The internal watchdog timer clears whenever RST asserts or a  
rising or falling edge on WDI is detected. The watchdog has an initial watchdog  
timeout period (35s min) after each reset event and a short timeout period  
(1.12s min) after the first valid WDI transition. Floating WDI does not disable the  
watchdog timer function.  
WDI  
Primary Supply-Voltage Input. V 1 provides power to the device when it is  
CC  
6
6
4
8
6
V
V
1
2
CC  
greater than V 2. V 1 is the input to the primary reset threshold monitor.  
CC  
CC  
Secondary Supply-Voltage Input. V 2 provides power to the device when it is  
CC  
—
CC  
greater than V 1. V 2 is the input to the secondary reset threshold monitor.  
CC  
CC  
Undervoltage Reset Comparator Input. RSTIN provides a high-impedance  
comparator input for the adjustable reset monitor. RST asserts low if the voltage  
—
—
7
RSTIN at RSTIN drops below the 626mV internal reference voltage. Connect a resistive  
voltage-divider to RSTIN to monitor voltages higher than 626mV. Connect  
RSTIN to V 1 or V 2 if unused.  
CC  
CC  
_______________________________________________________________________________________  
7
1...45678910...16

中文翻译

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