Datasheet > MAX6729AKAZGD4+T

MAX6729AKAZGD4+T

更新时间： 2023-02-26 12:57:23

品牌	Logo	应用领域
美信 - MAXIM		信息通信管理光电二极管
页数	文件大小	规格书
18页	1688K
描述
Power Management Circuit, BICMOS, PDSO8

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数据手册

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MAX6729AKAZGD4+T 数据手册

MAX6715A–MAX6729A/

MAX6797A

Dual/Triple, Ultra-Low-Voltage, SOT23 μP

Supervisory Circuits

Typical Operating Characteristics (continued)

= 5V, V

= 3.3V, T = +25°C, unless otherwise noted.)

CC1

CC2 A

RSTIN INPUT TO RESET OUTPUT DELAY

vs. TEMPERATURE

POWER-FAIL INPUT TO POWER-FAIL

OUTPUT DELAY vs. TEMPERATURE

MR TO RESET OUTPUT DELAY

MAX6715A-29A toc12

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

30mV OVERDRIVE

2V/div

RST

2V/div

-40 -25 -10

20 35 50 65 80 95 110 125

-40 -25 -10

20 35 50 65 80 95 110 125

50ns/div

TEMPERATURE (°C)

Pin Description

MAX6728A/

MAX6727A MAX6729A/

MAX6797A

NAME

FUNCTION

MAX6715A/ MAX6717A/ MAX6719A/ MAX6721A/ MAX6723A/ MAX6725A/

MAX6716A MAX6718A MAX6720A MAX6722A MAX6724A MAX6726A

Active-Low Reset Output,

Open-Drain or Push-Pull.

RST/RST1 changes from

high to low when V

CC1

or V

drops below the

CC2

selected reset thresholds,

RSTIN is below threshold,

MR is pulled low, or the

watchdog triggers a reset.

RST/ RST/RST1 remains low for

RST1 the reset timeout period

1, 4

after V

/RSTIN

CC1 CC2

exceed the device reset

thresholds, MR goes low

to high, or the watchdog

triggers a reset. Open-

drain outputs require an

external pullup resistor.

Push-pull outputs are

referenced to V

CC1

Maxim Integrated

│ 6

www.maximintegrated.com

1...3 4 567 8 9...18

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