MAX6715A–MAX6729A/
MAX6797A
Dual/Triple, Ultra-Low-Voltage, SOT23 μP
Supervisory Circuits
Electrical Characteristics (continued)
(V
= 0.8V to 5.5V, V
= 0.8V to 5.5V, GND = 0V, T = -40°C to +125°C, unless otherwise noted. Typical values are at T
=
CC1
CC2
A
A
+25°C.) (Note 1)
PARAMETER
SYMBOL
ΔV /°C
CONDITIONS
MIN
TYP
20
MAX
UNITS
ppm/°C
%
Reset Threshold Tempco
TH
Reset Threshold Hysteresis
V
Referenced to V typical
0.5
HYST
TH
V
V
= (V
= (V
+ 100mV) to (V
- 100mV) or
- 75mV)
CC1
CC2
TH1
TH2
TH1
V
to Reset Output Delay
t
20
µs
CC
RD
+ 75mV) to (V
TH2
D1
D2
1.1
8.8
1.65
13.2
26.25
52.5
210
2.2
17.6
35
D7 (MAX6797A only)
17.5
35
D8 (MAX6797A only)
70
Reset Timeout Period
t
ms
RP
D3
D5
D6
D4
140
280
560
1120
280
560
1120
2240
420
840
1680
ADJUSTABLE RESET COMPARATOR INPUT (MAX6719A/MAX6720A/MAX6723A–MAX6727A)
RSTIN Input Threshold
RSTIN Input Current
V
611
626.5
642
mV
nA
mV
µs
RSTIN
I
-100
+100
RSTIN
RSTIN Hysteresis
3
RSTIN to Reset Output Delay
t
V
to (V - 30mV)
RSTIN
22
RSTIND
RSTIN
POWER-FAIL INPUT (MAX6728A/MAX6729A)
PFI Input Threshold
PFI Input Current
PFI Hysteresis
V
611
626.5
642
mV
nA
mV
µs
PFI
I
V
t
-100
+100
PFI
3
PFH
PFI to PFO Delay
(V
+ 30mV) to (V - 30mV)
PFI
2
DPF
PFI
MANUAL-RESET INPUT (MAX6715A–MAX6722A/MAX6725A–MAX6729A)
V
0.3 x V
CC1
IL
MR Input Voltage
V
V
0.7 x V
IH
CC1
MR Minimum Pulse Width
MR Glitch Rejection
MR to Reset Delay
1
µs
ns
ns
kΩ
100
200
50
t
MR
MR Pullup Resistance
25
80
WATCHDOG INPUT (MAX6721A–MAX6729A)
First watchdog period after reset timeout
period
35
54
72
Watchdog Timeout Period
t
s
WD
Normal mode
(Note 2)
1.12
50
1.68
2.24
WDI Pulse Width
WDI Input Voltage
WDI Input Current
t
ns
V
WDI
V
0.3 x V
0.7 x V
-1
IL
CC1
V
IH
CC1
I
V
= 0V or V
CC1
+1
µA
WDI
WDI
Maxim Integrated
│
3
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