MAX6316–MAX6322
5-Pin μP Supervisory Circuits with
Watchdog and Manual Reset
P-channel transistor on-resistance quickly charges stray
capacitance on the reset line, allowing RESET to transi-
tion from low to high within the required two electronic-
clock cycles, even with several devices on the reset line.
This process occurs regardless of whether the reset was
ter a logic low (see Electrical Characteristics), and small
enough to register a logic high while supplying all input
current and leakage paths connected to the RESET line.
A 10kΩ pullup is sufficient in most applications.
Manual-Reset Input
caused by V
dipping below the reset threshold, the
CC
The MAX6316_/MAX6317H/MAX6319_H/MAX6320P/
MAX6322HP feature a manual reset input. A logic low on
MR asserts a reset. After MR transitions low to high, reset
remains asserted for the duration of the reset timeout
watchdog timing out, MR being asserted, or the μP or
other device asserting RESET. The parts do not require
an external pullup. To minimize supply current con-
sumption, the internal 4.7kΩ pullup resistor disconnects
from the supply whenever the MAX6316M/MAX6318MH/
MAX6319MH assert reset.
period (t ). The MR input is connected to V
through
RP
CC
an internal 52kΩ pullup resistor and therefore can be left
unconnected when not in use. MR can be driven with
TTL-logic levels in 5V systems, with CMOS-logic levels in
3V systems, or with open-drain or open-collector output
devices. A normally-open momentary switch from MR to
ground can also be used; it requires no external debounc-
ing circuitry. MR is designed to reject fast, negative-going
transients (typically 100ns pulses). A 0.1μF capacitor from
MR to ground provides additional noise immunity.
Open-Drain RESET Output
The MAX6320P/MAX6321HP/MAX6322HP have an
active-low, open-drain reset output. This output structure
will sink current when RESET is asserted. Connect a pul-
lup resistor from RESET to any supply voltage up to 6V
(Figure 6). Select a resistor value large enough to regis-
The MR input pin is equipped with internal ESD-protection
circuitry that may become forward biased. Should MR
V
CC
t
0.8 x V
RP
CC
be driven by voltages higher than V , excessive cur-
RESET
CC
OR
rent would be drawn, which would damage the part. For
example, assume that MR is driven by a +5V supply other
µC RESET DELAY
0.7V
than V . If V
maximum rating is violated [-0.3V to (V
drops lower than +4.7V, MR’s absolute
CC
CC
t
R
t
S
+ 0.3V)], and
CC
undesirable current flows through the ESD structure from
MR to V . To avoid this, use the same supply for MR as
ACTIVE
PULLUP
TURNS ON
RESET PULLED LOW
BY µC OR
RESET GENERATOR
CC
the supply monitored by V . This guarantees that the
CC
voltage at MR will never exceed V
.
CC
Figure 5. Bidirectional RESET Timing Diagram
Watchdog Input
The MAX6316_/MAX6317H/MAX6318_H/MAX6320P/
MAX6321HP feature a watchdog circuit that monitors the
μP’s activity. If the μP does not toggle the watchdog input
+3.3V
+5.0V
(WDI) within the watchdog timeout period (t ), reset
WD
asserts. The internal watchdog timer is cleared by reset
or by a transition at WDI (which can detect pulses as
short as 50ns). The watchdog timer remains cleared while
reset is asserted. Once reset is released, the timer begins
counting again (Figure 7).
V
CC
MR*
10kΩ
WDI**
RESET
5V SYSTEM
RESET***
The WDI input is designed for a three-stated output
device with a 10μA maximum leakage current and the
capability of driving a maximum capacitive load of 200pF.
The three-state device must be able to source and sink at
least 200μA when active. Disable the watchdog function
by leaving WDI unconnected or by three-stating the driver
connected to WDI. When the watchdog timer is left open
circuited, the timer is cleared internally at intervals equal
to 7/8 of the watchdog period.
MAX6320
MAX6321
MAX6322
GND
* MAX6320/MAX6322
** MAX6320/MAX6321
*** MAX6321/MAX6322
Figure 6. MAX6320P/MAX6321HP/MAX6322HP Open-Drain
RESET Output Allows Use with Multiple Supplies
Maxim Integrated
│ 9
www.maximintegrated.com
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