EVALUATION KIT AVAILABLE
MAX5713/MAX5714/MAX5715
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and SPI Interface
General Description
Benefits and Features
The MAX5713/MAX5714/MAX5715 4-channel, low-power,
8-/10-/12-bit, voltage-output digital-to-analog converters
(DACs) include output buffers and an internal reference
that is selectable to be 2.048V, 2.500V, or 4.096V. The
MAX5713/MAX5714/MAX5715 accept a wide supply
voltage range of 2.7V to 5.5V with extremely low power
(3mW) consumption to accommodate most low-voltage
applications. A precision external reference input allows
rail-to-rail operation and presents a 100kI (typ) load to
an external reference.
S Four High-Accuracy DAC Channels
ꢀ12-Bit Accuracy Without Adjustment
ꢀ1 ꢀLB ꢁIꢀ Buꢂꢂered ꢃoltage ꢄutꢅut
ꢀMonotonic ꢄver All ꢄꢅerating Conditions
ꢀꢁndeꢅendent Mode Lettings ꢂor Each DAC
S Three Precision Lelectable ꢁnternal Reꢂerences
ꢀ2.048ꢃ, 2.500ꢃ, or 4.096ꢃ
S ꢁnternal ꢄutꢅut Buꢂꢂer
ꢀRail-to-Rail ꢄꢅeration with External Reꢂerence
ꢀ4.5µs Lettling Time
The MAX5713/MAX5714/MAX5715 have a 50MHz 3-wire
SPI/QSPI™/MICROWIRE®/DSP-compatible serial interface
that also includes a RDY output for daisy-chain applica-
tions. The DAC output is buffered and has a low supply
current of less than 250FA per channel and a low off-
set error of Q0.5mV (typ). On power-up, the MAX5713/
MAX5714/MAX5715 reset the DAC outputs to zero, pro-
viding additional safety for applications that drive valves
or other transducers which need to be off on power-up.
The internal reference is initially powered down to allow
use of an external reference. The MAX5713/MAX5714/
MAX5715 allow simultaneous output updates using soft-
ware LOAD commands or the hardware load DAC logic
input (LDAC).
ꢀꢄutꢅuts Directly Drive 2kI ꢀoads
S Lmall 5mm x 4.4mm 14-Pin TLLꢄP or Ultra-Lmall
1.6mm x 2.2mm 12-Bumꢅ WꢀP Package
S Wide 2.7ꢃ to 5.5ꢃ Luꢅꢅly Range
S Leꢅarate 1.8ꢃ to 5.5ꢃ ꢃ
Power-Luꢅꢅly ꢁnꢅut
DDꢁꢄ
S 50MHz 3-Wire LPꢁ/QLPꢁ/MꢁCRꢄWꢁRE/DLP
Comꢅatible Lerial ꢁnterꢂace with RDY ꢄutꢅut
S Power-ꢄn-Reset to Zero-Lcale DAC ꢄutꢅut
S LDAC and CLR For Asynchronous Control
S Three Loꢂtware-Lelectable Power-Down ꢄutꢅut
ꢁmꢅedances
ꢀ1kI, 100kI, or High ꢁmꢅedance
A clear logic input (CLR) allows the contents of the CODE
and the DAC registers to be cleared asynchronously and
sets the DAC outputs to zero. The MAX5713/MAX5714/
MAX5715 are available in a 14-pin TSSOP and an ultra-
small, 12-bump WLP package and are specified over the
-40NC to +125NC temperature range.
Functional Diagram
V
DDIO
V
REF
DD
MAX5713
MAX5714
MAX5715
INTERNAL REFERENCE/
EXTERNAL BUFFER
CSB
SCLK
DIN
Applications
1 OF 4 DAC CHANNELS
BUFFER
CODE
REGISTER
DAC
LATCH
8-/10-/12-BIT
DAC
Programmable Voltage and Current Sources
Gain and Offset Adjustment
OUTA
OUTB
OUTC
OUTD
SPI SERIAL
INTERFACE
(RDY)
CLR
Automatic Tuning and Optical Control
Power Amplifier Control and Biasing
Process Control and Servo Loops
Portable Instrumentation
CLEAR/
RESET
CLEAR/
RESET
CODE
LOAD
100kI
1kI
(LDAC)
POWER-DOWN
DAC CONTROL LOGIC
POR
GND
Data Acquisition
( ) TSSOP PACKAGE ONLY
Ordering Information appears at end of data sheet.
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corporation.
For related parts and recommended products to use with this part,
refer to: www.maximintegrated.com/MAX5713.related
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-6394; Rev 3; 6/13