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MAX3940E/D

更新时间： 2024-02-15 13:24:55
品牌 Logo 应用领域
美信 - MAXIM 驱动器
页数 文件大小 规格书
13页 352K
描述
10Gbps EAM Driver with Integrated Bias Network

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中文翻译

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MAX3940E/D 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIE包装说明：DIE-44
针数：44Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.87
应用程序：SONET;SDHJESD-30 代码：R-XUUC-N44
JESD-609代码：e0湿度敏感等级：3
负电源额定电压：-5.2 V功能数量：1
端子数量：44最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：DIE封装形状：RECTANGULAR
封装形式：UNCASED CHIP峰值回流温度（摄氏度）：240
认证状态：Not Qualified表面贴装：YES
技术：BIPOLAR电信集成电路类型：ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：NO LEAD端子位置：UPPER
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

MAX3940E/D 数据手册

 浏览型号MAX3940E/D的Datasheet PDF文件第1页浏览型号MAX3940E/D的Datasheet PDF文件第2页浏览型号MAX3940E/D的Datasheet PDF文件第4页浏览型号MAX3940E/D的Datasheet PDF文件第5页浏览型号MAX3940E/D的Datasheet PDF文件第6页浏览型号MAX3940E/D的Datasheet PDF文件第7页 
10Gbps EAM Driver with Integrated  
Bias Network  
ELECTRICAL CHARACTERISTICS (continued)  
(V = -5.5V to -4.9V, T = -40°C to +85°C. Typical values are at V = -5.2V, I  
= 30mA, I = 100mA, and T = +25°C, unless  
MOD A  
EE  
A
EE  
BIAS  
otherwise noted.)  
PARAMETER  
Modulation Set Bandwidth  
MODSET Input Resistance  
SYMBOL  
CONDITIONS  
MIN  
TYP  
5
MAX  
UNITS  
MHz  
Modulation depth 10%, 50Ω driver load,  
see Figure 2  
20  
kΩ  
Modulation-Current Temperature  
Stability  
(Note 6)  
-480  
+480  
ppm/°C  
Modulation-Current Setting Error  
Output Resistance  
50Ω driver load, T = +25°C  
-5  
+5  
%
A
R
OUT to GND  
42.5  
50  
58.5  
Ω
OUT  
BIASSET = V , MODEN = V , MODSET =  
EE  
EE  
Total Off Current  
1
mA  
dB  
V
, DATA+ = high, DATA- = low  
EE  
I
I
= 30mA,  
= 50mA  
BIAS  
MOD  
Output Return Loss  
RL  
≤ 5GHz  
8
OUT  
Output Edge Speed  
20% to 80% (Notes 6, 8)  
Figure 3 (Note 6)  
(Notes 6, 8)  
23  
32  
ps  
ps  
ps  
Setup/Hold Time  
t
, t  
SU HD  
25  
20  
Pulse-Width Adjustment Range  
50  
Pulse-Width Control Input Range  
(Single Ended)  
V
+
0.5  
V
+
EE  
1.5  
EE  
For PWC+ and PWC-  
(PWC+) - (PWC-)  
V
Pulse-Width Control Input Range  
(Differential)  
-0.5  
-10  
+0.5  
V
Output Overshoot  
δ
(Notes 6, 8)  
+10  
1.1  
14  
%
Driver Random Jitter  
Driver Deterministic Jitter  
CONTROL INPUTS  
RJ  
(Note 6)  
0.3  
6.8  
ps  
RMS  
DR  
DR  
DJ  
PWC- = GND (Notes 6, 9)  
ps  
P-P  
V
+
2.0  
EE  
Input High Voltage  
V
(Note 10)  
V
IH  
V
+
0.8  
EE  
Input Low Voltage  
Input Current  
V
(Note 10)  
(Note 10)  
V
IL  
-80  
+80  
µA  
Note 1: Supply current remains elevated once the retiming function has been enabled. Power must be cycled to reduce supply  
current after the retiming function has been disabled.  
Note 2: Power-supply noise rejection is specified as PSNR = 20Log(V  
/ ∆V  
). V  
is the voltage across a 50Ω load.  
OUT  
noise (on Vcc)  
OUT  
V
= 100mV  
.
noise (on Vcc)  
P-P  
Note 3: For DATA+, DATA-, CLK+, and CLK-.  
Note 4: CLK input characterized at 10.7Gbps  
Note 5: R  
= (V  
- V ) / I  
with MODEN = V , DATA+ = high, and DATA- = low.  
OUT EE  
BSEQV  
BIASSET  
EE  
Note 6: Guaranteed by design and characterization using the circuit shown in Figure 4.  
Note 7: R = (V - V ) / (I - 37mA) with BIASSET = V  
.
EE  
MODEQV  
MODSET  
EE  
OUT  
Note 8: 50Ω load, characterized at 10.7Gbps with a 1111 1111 0000 0000 pattern.  
Note 9: Deterministic jitter is defined as the arithmetic sum of PWD (pulse-width distortion) and PDJ (pattern-dependent jitter).  
7
Measured with a 10.7Gbps 2 - 1 PRBS pattern with eighty 0s and eighty 1s inserted in the data pattern.  
Note 10: For MODEN and PLRT.  
_______________________________________________________________________________________  
3
1234567...13

中文翻译

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