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MAX3875AEHJ

更新时间： 2024-01-21 19:44:33

品牌	Logo	应用领域
美信 - MAXIM		ATM集成电路 SONET集成电路 SDH集成电路电信集成电路电信电路异步传输模式时钟
页数	文件大小	规格书
8页	421K
描述
2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC

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技术参数
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MAX3875AEHJ 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	TFQFP,	针数：	32
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.42
JESD-30 代码：	S-PQFP-G32	JESD-609代码：	e0
长度：	5 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	32
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFQFP
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	245	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大压摆率：	167 mA
标称供电电压：	3.3 V	表面贴装：	YES
电信集成电路类型：	ATM/SONET/SDH CLOCK RECOVERY CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	5 mm

MAX3875AEHJ 数据手册

2.5Gbps, Low-Power, +3.3V

Clock Recovery and Data Retiming IC

Frequency Detector

The digital frequency detector (FD) aids frequency

acquisition during start-up conditions. The frequency dif-

ference between the received data and the VCO clock is

derived by sampling the in-phase and quadrature VCO

outputs on both edges of the data input signal.

Depending on the polarity of the frequency difference,

the FD drives the VCO until the frequency difference is

reduced to zero. Once frequency acquisition is com-

plete, the FD returns to a neutral state. False locking is

completely eliminated by this digital frequency detector.

H (j2πf) (dB)

C = 1.0µF

f = 2.6kHz

C = 0.1µF

f = 26kHz

Loop Filter and VCO

The phase detector and frequency detector outputs are

summed into the loop filter. An external capacitor, C , is

required to set the PLL damping ratio. Refer to Design

Procedure for guidelines on selecting this capacitor.

f (kHz)

100

1000

The loop filter output controls the on-chip LC VCO run-

ning at 2.488GHz. The VCO provides low phase noise

and is trimmed to the correct frequency. Clock jitter

Figure 4. Open-Loop Transfer Function

generation is typically 1.2ps

width of 12kHz to 20MHz.

within a jitter band-

RMS

H(j2πf) (dB)

Loss-of-Lock Monitor

A loss-of-lock (LOL) monitor is incorporated in the

MAX3875A frequency detector. A loss-of-lock condition

is signaled immediately with a TTL low. When the PLL is

frequency locked, LOL switches to TTL high in approxi-

mately 800ns.

C = 0.1µF

-3

C = 1.0µF

Note that the LOL monitor is only valid when a data

stream is present on the inputs to the MAX3875A. As a

result, LOL does not detect a loss-of-power condition

resulting from a loss of the incoming signal.

Design Procedure

f (kHz)

Setting the Loop Filter

The MAX3875A is designed for both regenerator and

receiver applications. Its fully integrated PLL is a classic

second-order feedback system, with a loop bandwidth

100

1000

Figure 5. Closed-Loop Transfer Function

(f ) fixed at 1.1MHz. The external capacitor, C , can be

For an overdamped system (f /f ) < 0.25, the jitter peak-

ing (M ) of a second-order system can be approxi-

Z L

adjusted to set the loop damping. Figures 4 and 5 show

the open-loop and closed-loop transfer functions.

mated by:

The PLL zero frequency, f , is a function of external

capacitor C , and can be approximated according to:





= 20log 1+









For example, using C = 0.1µF results in a jitter peaking

2π 60 C

(

)

of 0.2dB. Reducing C below 0.01µF may result in PLL

instability. The recommended value for C = 1.0µF to

guarantee a maximum jitter peaking of less than 0.1dB.

must be a low TC, high-quality capacitor of type

X7R or better.

_______________________________________________________________________________________

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