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MAX3875AEHJ

更新时间： 2024-01-29 02:00:35
品牌 Logo 应用领域
美信 - MAXIM ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式时钟
页数 文件大小 规格书
8页 421K
描述
2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC

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MAX3875AEHJ 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：TFQFP,针数：32
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.42
JESD-30 代码：S-PQFP-G32JESD-609代码：e0
长度：5 mm湿度敏感等级：1
功能数量：1端子数量：32
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TFQFP
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：245认证状态：Not Qualified
座面最大高度：1.2 mm最大压摆率：167 mA
标称供电电压：3.3 V表面贴装：YES
电信集成电路类型：ATM/SONET/SDH CLOCK RECOVERY CIRCUIT温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：5 mm

MAX3875AEHJ 数据手册

 浏览型号MAX3875AEHJ的Datasheet PDF文件第2页浏览型号MAX3875AEHJ的Datasheet PDF文件第3页浏览型号MAX3875AEHJ的Datasheet PDF文件第4页浏览型号MAX3875AEHJ的Datasheet PDF文件第5页浏览型号MAX3875AEHJ的Datasheet PDF文件第6页浏览型号MAX3875AEHJ的Datasheet PDF文件第8页 
2.5Gbps, Low-Power, +3.3V  
Clock Recovery and Data Retiming IC  
Input and Output Terminations  
The MAX3875A’s digital outputs (SDO+, SDO-,  
SCLKO+, SCLKO-) are designed to interface with PECL  
signal levels. It is important to bias these ports appropri-  
ately. A circuit that provides a Thevenin equivalent of  
System Loopback  
The MAX3875A is designed to allow system loopback  
testing. The user can connect a serializer output in a  
transceiver directly to the SLBI+ and SLBI- inputs of the  
MAX3875A for system diagnostics. To select the SLBI  
inputs, apply a TTL logic high to the SIS pin.  
50Ω to V  
- 2V can be used with fixed impedance  
CC  
transmission lines for proper termination. To ensure best  
performance, the differential outputs must have bal-  
anced loads. The input termination can be driven differ-  
entially, or can be driven single-ended by externally  
biasing SDI- or SLBI- to the center of the voltage swing.  
PECL Input Levels  
When interfacing with differential PECL input levels, it is  
important to attenuate the signal while still maintaining  
50Ω termination (Figure 6). AC coupling is also  
required to maintain the input common-mode level.  
Jitter Tolerance and Input  
Sensitivity Trade-Offs  
Layout  
The MAX3875A’s performance can be significantly  
affected by circuit board layout and design. Use good  
high-frequency design techniques, including minimiz-  
ing ground inductance and using fixed-impedance  
transmission lines on the data and clock signals.  
Power-supply decoupling should be placed as close to  
When the received data amplitude is higher than  
50mV , the MAX3875A provides a typical jitter toler-  
P-P  
ance of 0.45UI at jitter frequencies greater than 10MHz.  
The SDH/SONET jitter tolerance specification is 0.15UI,  
leaving a jitter allowance of 0.3UI for receiver preamplifi-  
er and postamplifier design.  
V
as possible. Take care to isolate the input from the  
CC  
The BER is better than 1 x 10-10 for input signals  
output signals to reduce feedthrough.  
greater than 10mV . At 10mV , jitter tolerance will  
P-P  
P-P  
be degraded, but will still be above the SDH/SONET  
requirement. The user can make a trade-off between jit-  
ter tolerance and input sensitivity according to the spe-  
cific application. Refer to the Typical Operating  
Characteristics for Jitter Tolerance and BER vs. Input  
Amplitude graphs.  
V
CC  
Applications Information  
50Ω  
50Ω  
Consecutive Identical Digits (CID)  
The MAX3875A has a low phase and frequency drift in  
the absence of data transitions. As a result, long runs of  
consecutive zeros and ones can be tolerated while  
maintaining a BER of 1 x 10-10. The CID tolerance is  
tested using a 213 - 1 PRBS, substituting a long run of  
zeros to simulate the worst case. A CID tolerance of  
2000 bits is typical.  
0.1µF  
25Ω  
SDI+  
PECL  
LEVELS  
100Ω  
0.1µF  
SDI-  
25Ω  
Phase Adjust  
The internal clock is aligned to the center of the data  
eye. For specific applications this sampling position  
can be shifted using the PHADJ inputs to optimize BER  
performance. The PHADJ inputs operate with differen-  
tial input voltages up to 1.5V. A simple resistor-divider  
with a bypass capacitor is sufficient to set these levels.  
When the PHADJ inputs are not used, they should be  
MAX3875A  
Figure 6. PECL Input Interface  
tied directly to V  
.
CC  
_______________________________________________________________________________________  
7
1...45678

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