Datasheet > 电信电路 > ATM/SONET/SDH 集成电路> MAX3875AEHJ

MAX3875AEHJ

更新时间： 2024-01-19 20:47:33

品牌	Logo	应用领域
美信 - MAXIM		ATM集成电路 SONET集成电路 SDH集成电路电信集成电路电信电路异步传输模式时钟
页数	文件大小	规格书
8页	421K
描述
2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC

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技术参数
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MAX3875AEHJ 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	TFQFP,	针数：	32
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.42
JESD-30 代码：	S-PQFP-G32	JESD-609代码：	e0
长度：	5 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	32
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFQFP
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	245	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大压摆率：	167 mA
标称供电电压：	3.3 V	表面贴装：	YES
电信集成电路类型：	ATM/SONET/SDH CLOCK RECOVERY CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	5 mm

MAX3875AEHJ 数据手册

2.5Gbps, Low-Power, +3.3V

Clock Recovery and Data Retiming IC

Pin Description (continued)

NAME

SCLKO+

SDO-

FUNCTION

Positive Serial Clock Output, PECL, 2.488GHz. SDO+ is clocked out on the rising edge of SCLKO+.

Negative Data Output, PECL compatible, 2.488Gbps

SDO+

LOL

Positive Data Output, PECL compatible, 2.488Gbps

Loss-of-Lock Output, TTL, PLL loss-of-lock monitor, active low (internal 10kΩ pull-up resistor)

PHADJ-

PHADJ+

FIL-

Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to V

if not used.

Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to V

if not used.

Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.

Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.

FIL+

SIS

PHADJ+ PHADJ-

FIL+ FIL-

SDO+

SDO-

SDI+

SDI-

CML

AMP

PHASE AND

FREQUENCY

DETECTOR

SCLKO+

SCLKO-

MUX

LOOP

FILTER

VCO

SLBI+

SLBI-

LOL

MAX3875A

TTL

Figure 3. Functional Diagram

800mV . The bit error rate is better than 1 x 10^-10for

P-P

input signals as small as 10mVp-p, although the jitter

tolerance performance will be degraded. For interfacing

with PECL signal levels, see Applications Information.

Detailed Description

The MAX3875A consists of a fully integrated phase-

locked loop (PLL), input amplifier, data retiming block,

and PECL output buffer (Figure 3). The PLL consists of

a phase/frequency detector (PFD), a loop filter, and a

voltage-controlled oscillator (VCO).

Phase Detector

The phase detector incorporated in the MAX3875A pro-

duces a voltage proportional to the phase difference

between the incoming data and the internal clock.

Because of its feedback nature, the PLL drives the

error voltage to zero, aligning the recovered clock to

the center of the incoming data eye for retiming. The

external phase adjust pins (PHADJ+, PHADJ-) allow the

user to vary the internal phase alignment.

This device is designed to deliver the best combination

of jitter performance and power dissipation by using a

fully differential signal architecture and low-noise

design techniques.

Input Amplifier

Input amplifiers are implemented for both the main data

and system loopback inputs. These amplifiers accept a

differential input amplitude from 50mV

up to

P-P

_______________________________________________________________________________________

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与MAX3875AEHJ相关器件

型号	品牌	描述	获取价格	数据表
MAX3875E/D	MAXIM	2.5Gbps, Low-Power, #.3V Clock Recovery and Data Retiming IC	获取价格
MAX3875EHJ	MAXIM	2.5Gbps, Low-Power, #.3V Clock Recovery and Data Retiming IC	获取价格
MAX3875EHJ+	MAXIM	Clock Recovery Circuit, 1-Func, PQFP32, 5 X 5 MM, 1 MM HEIGHT, ROHS COMPLIANT, MO-136AA, T	获取价格
MAX3875EVKIT	MAXIM	Low-Cost.Precision.High-Side Current-Sense Amplifier[MAX4172/MAX4172ESA/MAX4172ESA-T/MAX41	获取价格
MAX3876	MAXIM	2.5Gbps, Low-Power, #.3V Clock Recovery and Data Retiming IC	获取价格
MAX3876E/D	MAXIM	2.5Gbps, Low-Power, #.3V Clock Recovery and Data Retiming IC	获取价格

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