+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator
DC ꢀLꢀCTꢁICAL CHAꢁACTꢀꢁISTICS (continued)
(V
= +3.0V to +3.6V, LVDS differential load = 100Ω ±1ꢂ, CML load = ꢀ0Ω ±1ꢂ to V , all TTL inputs are open, T = 0°C to
CC
CC A
+8ꢀ°C, unless otherwise noted. Typical values are at T = +2ꢀ°C and V
= +3.3V.)
A
CC
PAꢁAMꢀTꢀꢁ
TTL INPUTS AND OUTPUTS
Input Voltage High
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
IH
2.0
V
V
Input Voltage Low
V
IL
0.8
-ꢀ0
Input Current High
I
IH
V
V
= 2.0V
= 0
-2ꢀ0
-ꢀꢀ0
2.4
µA
µA
V
IH
Input Current Low
I
IL
-100
IL
Output Voltage High
Output Voltage Low
Output Impedance
V
OH
I
I
= 20µA
= 2mA
OH
OL
V
OL
0.4
V
6
ꢁΩ
TRIEN = GND
Note 2: When TEST = GND, the pattern generator will consume an additional 30mA.
Note 3: Guaranteed by design and characterization.
AC ꢀLꢀCTꢁICAL CHAꢁACTꢀꢁISTICS
CC
(V
= +3.0V to +3.6V, LVDS differential load = 100Ω ±1ꢂ, CML load = ꢀ0Ω ±1ꢂ to V , all TTL inputs are open, T = 0°C to
CC A
= +3.3V.) (Note 4)
+8ꢀ°C, unless otherwise noted. Typical values are at T = +2ꢀ°C and V
A
CC
PAꢁAMꢀTꢀꢁ
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
4:1 MULTIPLꢀXꢀꢁ WITH CLOCK GꢀNꢀꢁATOꢁ
Parallel Input Data Rate
622.08
±±.ꢀ
Mbps
ns
Maximum Parallel Input Sꢁew
Serial-Data Output Rate
t
(Note ꢀ)
es
2.48832
Gbps
ps
Serial-Data Output Rise/Fall Time
t , t
r
20ꢂ to 80ꢂ
(Note 6)
120
3.ꢀ
40
f
ps
RMS
Serial-Data Output Random Jitter
SRJ
SDJ
ps
p-p
Serial-Data Output Deterministic
Jitter
(Note ±)
8
18
ps
p-p
1:4 DꢀMULTIPLꢀXꢀꢁ
Serial-Data Input Rate
Serial-Data Setup Time
Serial-Data Hold Time
Parallel-Data Output Rate
2.48832
Gbps
ps
t
Figure 3
Figure 3
100
100
SU
t
ps
H
PDO±
622.08
622.08
1ꢀꢀ.ꢀ2
90
Mbps
MAX3831
MAX3832
Parallel-Clocꢁ Output Frequency
PCLKO±
MHz
PCLKO to PDO_ Delay
t
MAX3831, Figure 3
20ꢂ to 80ꢂ
-100
300
3ꢀ0
6ꢀ
ps
ps
ps
ps
ns
CLK-Q
LVDS Output Rise/Fall Time
LVDS Differential Sꢁew
t
t
Any differential pair
PDO1± to PDO4±
SKEW1
LVDS Channel-to-Channel Sꢁew
LVDS Three-State Enable Time
<100
30
SKEW2
Note 4: AC characteristics are guaranteed by design and characterization.
Note 5: Relative to the positive edge of the 1ꢀꢀMHz reference clocꢁ. PDI1 to PDI4 aligned to RCLKI at reset.
Note 6: Measured with a reference clocꢁ jitter of <1ps
.
RMS
Note ±: Deterministic jitter is the arithmetic sum of pattern-dependent jitter and pulse-width distortion.
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3