Compact 155Mbps to 4.25Gbps
Limiting Amplifier
MAX3748
CML Output Buffer
Hybrid Lead-Free Package
The MAX3748HETE is in a hybrid lead-free package.
The hybrid part contains leaded bumps in a lead-free
thin QFN package. The part is not 100% lead-free;
however, the high-lead solder in the internal portion of
the part does meet the RoHS exemption for high-lead
solders. For more information, visit www.maxim-
ic.com/emmi/.
The MAX3748 limiting amplifier’s CML output provides
high tolerance to impedance mismatches and inductive
connectors. The output current is approximately 18mA.
The output is disabled by connecting the DISABLE pin
to V . If the LOS pin is connected to the DISABLE pin,
CC
the outputs OUT+ and OUT- are at a static voltage
(squelch) whenever the input signal level drops below
the LOS threshold. The output buffer can be AC- or DC-
coupled to the load (Figure 4).
Design Procedure
Program the LOS Assert Threshold
Power-Detect and
Loss-of-Signal Indicator
External resistor R programs the LOS threshold. See
TH
the Assert/Deassert Levels vs. R graph in the Typical
TH
The MAX3748 is equipped with an LOS circuitry, which
indicates when the input signal is below a programma-
Operating Characteristics to select the appropriate
resistor.
ble threshold, set by resistor R
at the TH pin (see
TH
Typical Operating Characteristics for appropriate resis-
tor sizing). An averaging peak-power detector com-
pares the input signal amplitude with this threshold and
feeds the signal detect information to the LOS output,
Select the Coupling Capacitor
When AC-coupling is desired, coupling capacitors C
IN
and C
should be selected to minimize the receiv-
OUT
er’s deterministic jitter. Jitter is decreased as the input
which is open collector. Two control voltages, V
ASSERT
low-frequency cutoff (f ) is decreased:
IN
and V
, define the LOS assert and deassert
DEASSERT
f
= 1 / [2π(50)(C )]
IN
IN
levels. To prevent LOS chatter in the region of the pro-
grammed threshold, approximately 2dB of hysteresis is
built into the LOS assert/deassert function. Once assert-
ed, LOS is not deasserted until the input amplitude rises
For ATM/SONET or other applications using scrambled
NRZ data, select (C , C ) ≥ 0.1µF, which provides
IN
OUT
f
< 32kHz. For Fibre Channel, Gigabit Ethernet, or
IN
to the required level (V ) (Figure 5).
DEASSERT
other applications using 8B/10B data coding, select
(C , C
) ≥ 0.01µF, which provides f < 320kHz.
IN
OUT
IN
Refer to Application Note HFAN-1.1: Choosing AC-
Coupling Capacitors.
V
CC
V
CC
50Ω
50Ω
OUT+
OUT-
LOS
Q3
Q4
Q1
Q2
ESD
STRUCTURES
DISABLE
DATA
ESD
STRUCTURE
18mA
18mA
DISABLE
DISABLE
GND
Figure 5. MAX3748 LOS Output Circuit
Figure 4. CML Output Buffer
_______________________________________________________________________________________
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