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MAX34460ETM+

更新时间： 2024-02-29 06:52:49
品牌 Logo 应用领域
美信 - MAXIM /
页数 文件大小 规格书
65页 1774K
描述
Power Supply Management Circuit, PQCC48,

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MAX34460ETM+ 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：QCCN, LCC48,.24SQ,16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：12 weeks
风险等级：2.22模拟集成电路 - 其他类型：POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码：S-PQCC-N48湿度敏感等级：1
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QCCN封装等效代码：LCC48,.24SQ,16
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
认证状态：Not Qualified子类别：Power Management Circuits
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子形式：NO LEAD
端子节距：0.4 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

MAX34460ETM+ 数据手册

 浏览型号MAX34460ETM+的Datasheet PDF文件第58页浏览型号MAX34460ETM+的Datasheet PDF文件第59页浏览型号MAX34460ETM+的Datasheet PDF文件第60页浏览型号MAX34460ETM+的Datasheet PDF文件第62页浏览型号MAX34460ETM+的Datasheet PDF文件第63页浏览型号MAX34460ETM+的Datasheet PDF文件第64页 
MAX34460  
PMBus 12-Channel Voltage Monitor and Sequencer  
MFR_WATCHDOG_CONFIG (FDh)  
The MFR_WATCHDOG_CONFIG command is used  
to configure the external watchdog function. The  
MFR_WATCHDOG_CONFIG command is described in  
Table 40.  
Open-Drain Pins  
MSDA, MSCL, SCL, SDA, FAULT, and ALERT are open-  
drain pins and require external pullup resistors con-  
nected to V  
to realize high logic levels.  
DD  
PSEN0–PSEN11 can be user-configured as either CMOS  
push-pull or open-drain outputs. When configured as  
open-drain (see MFR_PSEN_CONFIG), external pullup  
Applications Information  
resistors connected to V  
logic levels.  
are required to realize high  
DD  
V
, V  
, and REG18 Decoupling  
DD  
DDA  
To achieve the best results when using the device,  
decouple V and V power inputs each with a  
Keep-Alive Circuit  
DD  
DDA  
In systems where the power to the device may be not  
always be present, a keep-alive circuit consisting of a  
Schottky diode and a bulk capacitor can be added to  
allow the device time to orderly shut down the power  
supplies it is controlling before power is lost.  
0.1FF capacitor. If possible, use a high-quality, ceramic,  
surface-mount capacitor. Surface-mount components  
minimize lead inductance, which improves performance;  
ceramic capacitors tend to have adequate high-frequen-  
cy response for decoupling applications. Decouple the  
REG18 regulator output using 1FF and 10nF capacitors  
with a maximum ESR of 500mI.  
Table 40. MFR_WATCHDOG_CONFIG  
BIT  
15:13  
12  
NAME  
MEANING  
These bits define the watchdog startup time.  
000  
001  
010  
011  
1s  
2s  
4s  
8s  
100  
101  
110  
111  
16s  
32s  
64s  
WD_STARTUP[2:0]  
0
128s  
This bit always returns a 0.  
These bits define the watchdog timeout time.  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
5ms  
10ms  
20ms  
40ms  
80ms  
160ms  
320ms  
640ms  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
1s  
2s  
4s  
11:8  
WD_TIMEOUT[3:0]  
8s  
16s  
32s  
64s  
128s  
7:4  
3
0
These bits always return a 0 when read.  
0 = WDO pin is watchdog output only.  
1 = WDO pin is watchdog output and manual-reset input.  
WD_WDO_MR  
When this bit is set to a 1, it resets the watchdog the same as a rising edge on  
WDI does. This bit always returns a 0 when read.  
2
1
0
WD_TOGGLE  
WD_MODE  
0 = Independent mode.  
1 = Dependent mode.*  
0 = Watchdog disabled (WDO is forced high impedance).  
1 = Watchdog enabled.  
WD_ENABLE  
*If dual sequencing is enabled, only the primary group is used to time the start of the watchdog.  
Maxim Integrated  
61  
 
 
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