Datasheet > MAX3180-MAX3183

MAX3180-MAX3183

更新时间： 2022-11-27 21:10:26

品牌	Logo	应用领域
美信 - MAXIM		/
页数	文件大小	规格书
6页	139K
描述
+3V to +5.5V, 1.5Mbps RS-232 Receivers in SOT23-5

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MAX3180-MAX3183 数据手册

+3V to +5.5V, 1.5Mbps

RS-232 Receivers in SOT23-5

0–MAX183

Signal Invalid Detector

Detailed Description

If no valid signal levels appear on RIN for 30µs (typ),

INVALID goes low. This event typically occurs if the RS-

232 cable is disconnected or if the connected peripher-

al transmitter is turned off. INVALID goes high when a

valid level is applied to the RS-232 receiver input.

Figure 2 shows the input levels and timing diagram for

INVALID operation.

The MAX3180–MAX3183 are EIA/TIA-232 and V.28/

V.24 communications receivers that convert RS-232

signals to CMOS logic levels. The devices operate on a

supply voltage of +3V to +5.5V and have a 1.5Mbps

data rate capability. They achieve a 0.5µA typical sup-

ply current. The MAX3180/MAX3182 have a receiver

enable control (EN), while the MAX3181/MAX3183 con-

tain a signal invalid output (INVALID). The MAX3180/

MAX3181 invert the ROUT signal relative to RIN. The

MAX3182/MAX3183 are not inverted. The devices

come in SOT23-5 packages.

Enable Input

The MAX3180/MAX3182 feature an enable input. Drive

EN high to force ROUT into a high-impedance state. In

this state, the devices ignore incoming RS-232 signals.

Drive EN low for normal operation.

Power-Supply Decoupling

In most circumstances, a 0.1µF V

bypass capacitor

is adequate for power-supply decoupling. Connect the

RIN

50%

bypass capacitor as close to the IC as possible.

PLH

PHL

ROUT

50%

Chip Information

TRANSISTOR COUNT: 41

Figure 1. Receiver Propagation-Delay Timing

VALID SIGNALS (INVALID = 1)

+2.7V

RECEIVER

INPUT

VOLTAGE

(V)

INVALID

REGION

INDETERMINATE

+0.3V

INVALID SIGNALS (INVALID = 0)

-0.3V

INVALID

OUTPUT

(V)

INDETERMINATE

-2.7V

INVH

INVL

VALID SIGNALS (INVALID = 1)

Figure 2. Input Levels and INVALID Timing

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