MAX24705, MAX24710
Table of Contents
1.
2.
3.
APPLICATION EXAMPLES.......................................................................................................... 6
BLOCK DIAGRAM........................................................................................................................ 6
DETAILED FEATURES................................................................................................................. 6
3.1 INPUT BLOCK FEATURES............................................................................................................... 6
3.2 DPLL FEATURES.......................................................................................................................... 7
3.3 APLL FEATURES.......................................................................................................................... 7
3.4 OUTPUT CLOCK FEATURES........................................................................................................... 7
3.5 GENERAL FEATURES .................................................................................................................... 7
4.
5.
PIN DESCRIPTIONS..................................................................................................................... 8
FUNCTIONAL DESCRIPTION .....................................................................................................11
5.1 DEVICE IDENTIFICATION AND PROTECTION....................................................................................11
5.2 TOP-LEVEL CONFIGURATION........................................................................................................11
5.2.1
5.2.2
APLL-Only Mode.................................................................................................................................. 11
DPLL+APLL Mode ............................................................................................................................... 12
5.3 LOCAL OSCILLATOR AND MASTER CLOCK CONFIGURATION............................................................14
5.3.1
5.3.1.1
5.3.2
5.3.3
External Oscillator................................................................................................................................ 14
Oscillator Characteristics to Minimize Output Jitter...................................................................... 14
On-Chip Crystal Oscillator ................................................................................................................... 15
Master Clock APLL Configuration........................................................................................................ 16
5.4 INPUT SIGNAL FORMAT CONFIGURATION.......................................................................................17
5.5 INPUT CLOCK DIVIDER, MONITOR AND SELECTOR .........................................................................17
5.5.1
5.5.2
5.5.2.1
5.5.2.2
5.5.2.3
5.5.2.4
Input Clock Frequency Dividers, Scaling and Inversion ...................................................................... 18
Input Clock Monitoring ......................................................................................................................... 18
Frequency Monitoring................................................................................................................... 18
Activity Monitoring......................................................................................................................... 19
Selected Reference Fast Activity Monitoring................................................................................ 20
External Monitoring....................................................................................................................... 20
Input Clock Priority, Selection and Switching ...................................................................................... 20
Priority Configuration .................................................................................................................... 20
Automatic Selection...................................................................................................................... 21
Forced Selection........................................................................................................................... 21
Ultra-Fast Reference Switching.................................................................................................... 21
External Reference Switching Mode ............................................................................................ 22
Output Clock Phase Continuity During Reference Switching....................................................... 22
5.5.3
5.5.3.1
5.5.3.2
5.5.3.3
5.5.3.4
5.5.3.5
5.5.3.6
5.6 DPLL ARCHITECTURE AND CONFIGURATION .................................................................................22
5.6.1
5.6.1.1
DPLL State Machine ............................................................................................................................ 22
Free-Run State ............................................................................................................................. 23
Prelocked State............................................................................................................................. 24
Locked State................................................................................................................................. 24
Loss-of-Lock State........................................................................................................................ 24
Prelocked 2 State ......................................................................................................................... 25
Holdover State .............................................................................................................................. 25
Mini-Holdover................................................................................................................................ 25
Bandwidth ............................................................................................................................................ 26
Damping Factor.................................................................................................................................... 26
Phase Detectors................................................................................................................................... 26
Loss of Phase Lock Detection ............................................................................................................. 27
Phase Monitor and Phase Build-Out.................................................................................................... 27
Phase Monitor............................................................................................................................... 27
Phase Build-Out in Response to Input Phase Transients ............................................................ 27
Automatic Phase Build-Out in Response to Reference Switching ............................................... 28
Manual Phase Build-Out Control .................................................................................................. 28
2
5.6.1.2
5.6.1.3
5.6.1.4
5.6.1.5
5.6.1.6
5.6.1.7
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.6.6.1
5.6.6.2
5.6.6.3
5.6.6.4
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