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MAX24705EXG2 PDF预览

MAX24705EXG2

更新时间: 2024-01-09 23:17:05
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟ATM异步传输模式外围集成电路晶体
页数 文件大小 规格书
121页 1606K
描述
ATM/SONET/SDH IC,

MAX24705EXG2 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:LBGA, BGA81,9X9,40Reach Compliance Code:unknown
风险等级:5.8JESD-30 代码:S-PBGA-B81
长度:10 mm端子数量:81
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:750 MHz封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装等效代码:BGA81,9X9,40
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE
主时钟/晶体标称频率:50 MHz座面最大高度:1.47 mm
最大压摆率:575 mA最大供电电压:1.89 V
最小供电电压:1.71 V标称供电电压:1.8 V
表面贴装:YES温度等级:INDUSTRIAL
端子形式:BALL端子节距:1 mm
端子位置:DUAL宽度:10 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

MAX24705EXG2 数据手册

 浏览型号MAX24705EXG2的Datasheet PDF文件第3页浏览型号MAX24705EXG2的Datasheet PDF文件第4页浏览型号MAX24705EXG2的Datasheet PDF文件第5页浏览型号MAX24705EXG2的Datasheet PDF文件第7页浏览型号MAX24705EXG2的Datasheet PDF文件第8页浏览型号MAX24705EXG2的Datasheet PDF文件第9页 
MAX24705, MAX24710  
1. Application Examples  
Figure 1-1. Synchronous Ethernet and SDH/SONET Line Card  
Synchronous Ethernet  
OC1P/N  
OC2P/N  
OC3P/N  
OC4P/N  
OC5P/N  
Clocks: any combination  
of 25M, 125M, 156.25M  
and related frequencies  
19.44M,  
25M, etc.  
From dual  
redundant  
timing functions  
IC1P/N  
IC2P/N  
Any combination of differential or  
2x single-ended signal format  
OC6P/N  
OC7P/N  
OC8P/N  
OC9P/N  
OC10P/N  
SDH/SONET Clocks:  
Nx6.48MHz to 622.08MHz  
local  
osc  
MCP/N  
2. Block Diagram  
Figure 2-1. Block Diagram  
DIV1  
DIV2  
DIV3  
DIV4  
DIV5  
DIV6  
DIV7  
DIV8  
DIV9  
DIV10  
OC1POS/NEG  
DPLL  
Hitless Switching,  
Jitter Filtering,  
Holdover  
APLL1  
3.7-4.2GHz,  
Sub-ps jitter,  
Fractional-N  
A
B
Input Block  
Scaler, Divider,  
Monitor  
OC2POS/NEG  
OC3POS/NEG  
OC4POS/NEG  
OC5POS/NEG  
OC6POS/NEG  
OC7POS/NEG  
OC8POS/NEG  
OC9POS/NEG  
OC10POS/NEG  
Figure 5-7  
Figure 5-8  
Figure 5-10  
MAX24710 only  
MAX24710 only  
C
D
APLL2  
3.7-4.2GHz,  
Sub-ps jitter,  
Fractional-N  
IC1POS/NEG  
IC2POS/NEG  
MCLKOSCP/N  
XIN  
XO  
XOUT  
SPI Interface  
JTAG  
and HW Control and Status Pins  
3. Detailed Features  
3.1  
Input Block Features  
Two input clocks, differential or CMOS/TTL signal format  
Input clocks can be any frequency from 2kHz up to 750MHz  
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTU-1, OTU-2, OTU-3  
Per-input fractional scaling (i.e. multiplying by ND where N is a 16-bit integer and D is a 32-bit integer and  
N<D) to undo 64B/66B and FEC scaling (e.g. 64/66, 238/255, 237/255, 236/255)  
All inputs constantly monitored by programmable activity monitors and frequency monitors  
Fast activity monitor can disqualify the selected reference after a few missing clock cycles  
Frequency measurement with 1.25ppm resolution  
Frequency monitor thresholds with 1.25ppm or 5ppb resolution  
6
 

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