19-3432; Rev 0; 11/04
1 2 -Bit , 1 2 5 Ms p s ADC w it h CMOS
Ou t p u t s fo r Wid e b a n d Ap p lic a t io n s
Ge n e ra l De s c rip t io n
Fe a t u re s
♦ 125Msps Conversion Rate
The MAX19541 monolithic 12-bit, 125Msps analog-to-
digital converter (ADC) is optimized for outstanding
d yna mic p e rforma nc e a t hig h-IF fre q ue nc ie s of
300MHz and beyond. This device operates with con-
version rates up to 125Msps while consuming only
861mW.
♦ SNR = 65dB, f = 100MHz at 125Msps
IN
♦ SFDR = 77dBc, f = 100MHz at 125Msps
IN
♦ ±0.7 LSB INL, ±0.25 DNL (typ)
♦ 861mW Power Dissipation at 125Msps
♦ On-Chip Selectable Divide-by-2 Clock Input
♦ Parallel or Demux Parallel Digital CMOS Outputs
♦ Reset Option for Synchronizing Multiple ADCs
♦ Data Clock Output
At 125Msps and an input frequency of 240MHz, the
MAX19541 achieves a spurious-free dynamic range
(SFDR) of 71.5dBc. The MAX19541 features an excel-
lent signal-to-noise ratio (SNR) of 65.4dB at 10MHz that
remains flat (within 3dB) for input tones up to 250MHz.
This makes the MAX19541 ideal for wideband applica-
tions such as power-amplifier predistortion in cellular
base-station transceiver systems.
♦ Offset Binary or Two’s-Complement Output
♦ Evaluation Kit Available (MAX19541EVKIT)
The MAX19541 operates in either parallel mode where
the data outputs appear on a single parallel port at the
sampling rate, or in demux parallel mode, where the out-
puts appear on two separate parallel ports at one-half
the sampling rate. See the Mode of Operation section.
Ord e rin g In fo rm a t io n
The MAX19541 operates on a single 1.8V supply. The
analog input is differential and can be AC- or DC-cou-
p le d . The ADC a ls o fe a ture s a s e le c ta b le on-c hip
divide-by-2 clock circuit that allows clock frequencies
as high as 250MHz. This helps to reduce the phase
noise of the input clock source, allowing for higher
dynamic performance. For best performance, a differ-
ential LVPECL sampling clock is recommended. The
digital outputs are CMOS compatible and the data for-
mat can be selected to be either two’s complement or
offset binary.
PIN-
PACKAGE
PKG
CODE
PART
TEMP RANGE
MAX19541EGK
-40°C to +85°C 68 QFN-EP*
G6800-4
EP = Exposed paddle.
P in Co n fig u ra t io n
TOP VIEW
A p in-c omp a tib le , 12-b it, 170Ms p s ve rs ion of the
MAX19541 is also available. Refer to the MAX19542
data sheet for more information.
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
AV
CC
1
2
3
4
5
6
7
8
9
51 DA4
50 DA3
49 DA2
48 DA1
47 DA0
46 ORB
45 OGND
AGND
REFIO
The MAX19541 is a va ila b le in a 68-p in QFN with
exposed paddle (EP) and is specified over the extend-
ed (-40°C to +85°C) temperature range.
REFADJ
AGND
AV
CC
AGND
INP
44 OV
CC
Ap p lic a t io n s
Base-Station Power Amplifier Linearization
INN
43 DCLKP
42 DCLKN
MAX19541
AGND 10
AV
CC
11
12
13
14
41 OV
CC
Cable Head-End Receivers
AV
CC
40 DB11
39 DB10
38 DB9
37 DB8
36 DB7
35 DB6
AV
CC
Wireless and Wired Broadband Communication
Communications Test Equipment
Radar and Satellite Subsystems
AV
CC
RESET 15
DEMUX 16
CLKDIV 17
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
NOTE: EXPOSED PADDLE CONNECTED TO AGND.
QFN
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.