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MAX19542

更新时间： 2024-10-03 11:18:11
品牌 Logo 应用领域
美信 - MAXIM /
页数 文件大小 规格书
23页 282K
描述
12-Bit, 170Msps ADC with CMOS Outputs for Wideband Applications

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MAX19542 数据手册

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19-3464; Rev 1; 10/10  
12-Bit, 170Msps ADC with CMOS  
Outputs for Wideband Applications  
MAX19542  
General Description  
Features  
The MAX19542 monolithic 12-bit, 170Msps analog-to-  
digital converter (ADC) is optimized for outstanding  
dynamic performance at high-IF frequencies of  
300MHz and beyond. This device operates with con-  
version rates up to 170Msps while consuming only  
907mW.  
o 170Msps Conversion Rate  
o SNR = 64.3dB, f = 100MHz at 170Msps  
o SFDR = 73dBc, f = 100MHz at 170Msps  
IN  
IN  
o
0.7 LSB INL, 0.25 DNL (typ)  
o 907mW Power Dissipation at 170Msps  
o On-Chip Selectable Divide-by-2 Clock Input  
o Parallel or Demux Parallel Digital CMOS Outputs  
o Reset Option for Synchronizing Multiple ADCs  
o Data Clock Output  
o Offset Binary or Two’s-Complement Output  
o Evaluation Kit Available (MAX19542EVKIT)  
At 170Msps and an input frequency of 240MHz, the  
MAX19542 achieves a spurious-free dynamic range  
(SFDR) of 76.4dBc. The MAX19542 features an excel-  
lent signal-to-noise ratio (SNR) of 65dB at 10MHz that  
remains flat (within 3dB) for input tones up to 250MHz.  
This makes the MAX19542 ideal for wideband applica-  
tions such as power-amplifier predistortion in cellular  
base-station transceiver systems.  
The MAX19542 operates in either parallel mode where  
the data outputs appear on a single parallel port at the  
sampling rate, or in demux parallel mode, where the out-  
puts appear on two separate parallel ports at one-half  
the sampling rate. See the Mode of Operation section.  
Ordering Information  
PART  
TEMP RANGE  
PIN-PACKAGE  
The MAX19542 operates on a single 1.8V supply. The  
analog input is differential and can be AC- or DC-cou-  
pled. The ADC also features a selectable on-chip  
divide-by-2 clock circuit that allows clock frequencies  
as high as 340MHz. This helps to reduce the phase  
noise of the input clock source, allowing for higher  
dynamic performance. For best performance, a differ-  
ential LVPECL sampling clock is recommended. The  
digital outputs are CMOS compatible and the data for-  
mat can be selected to be either two’s complement or  
offset binary.  
MAX19542EGK+  
-40°C to +85°C  
68 QFN-EP*  
+Denotes a lead(Pb)-free/RoHS-compliant package.  
*EP = Exposed pad.  
Pin Configuration  
TOP VIEW  
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52  
A pin-compatible, 12-bit, 125Msps version of the  
MAX19542 is also available. Refer to the MAX19541  
data sheet for more information.  
+
AVCC  
AGND  
REFIO  
REFADJ  
AGND  
AVCC  
AGND  
INP  
1
2
3
4
5
6
7
8
9
51 DA4  
50 DA3  
49 DA2  
48 DA1  
47 DA0  
46 ORB  
45 OGND  
44 OVCC  
43 DCLKP  
42 DCLKN  
41 OVCC  
40 DB11  
39 DB10  
38 DB9  
37 DB8  
36 DB7  
35 DB6  
The MAX19542 is available in a 68-pin QFN with  
exposed pad (EP) and is specified over the extended  
(-40°C to +85°C) temperature range.  
Applications  
INN  
MAX19542  
AGND 10  
AVCC 11  
AVCC 12  
AVCC 13  
AVCC 14  
RESET 15  
DEMUX 16  
CLKDIV 17  
Base-Station Power Amplifier Linearization  
Cable Head-End Receivers  
Wireless and Wired Broadband Communication  
Communications Test Equipment  
Radar and Satellite Subsystems  
EP  
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34  
NOTE: EXPOSED PAD CONNECTED TO AGND.  
QFN  
________________________________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,  
or visit Maxim’s website at www.maxim-ic.com.  
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