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MAX16122WTAK44+T PDF预览

MAX16122WTAK44+T

更新时间: 2024-02-08 11:56:25
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美信 - MAXIM 信息通信管理
页数 文件大小 规格书
16页 1243K
描述
Power Supply Support Circuit, Adjustable, 2 Channel, BICMOS

MAX16122WTAK44+T 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:VFBGA,Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.6其他特性:RESET THRESHOLD VOLTAGE IS 4.38 V
可调阈值:YES模拟集成电路 - 其他类型:POWER SUPPLY SUPPORT CIRCUIT
长度:1.235 mm信道数量:2
功能数量:1最高工作温度:125 °C
最低工作温度:-40 °C封装代码:VFBGA
峰值回流温度(摄氏度):NOT SPECIFIED座面最大高度:0.69 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.6 V
标称供电电压 (Vsup):3 V技术:BICMOS
温度等级:AUTOMOTIVE端子节距:0.4 mm
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:0.835 mm
Base Number Matches:1

MAX16122WTAK44+T 数据手册

 浏览型号MAX16122WTAK44+T的Datasheet PDF文件第4页浏览型号MAX16122WTAK44+T的Datasheet PDF文件第5页浏览型号MAX16122WTAK44+T的Datasheet PDF文件第6页浏览型号MAX16122WTAK44+T的Datasheet PDF文件第8页浏览型号MAX16122WTAK44+T的Datasheet PDF文件第9页浏览型号MAX16122WTAK44+T的Datasheet PDF文件第10页 
MAX16122–MAX16125  
Dual Pushbutton Controllers in  
Tiny 6-Bump WLP Package  
Bump Description (continued)  
BUMP  
NAME  
FUNCTION  
MAX16122/ MAX16124/  
MAX16123  
MAX16125  
Power-Supply Input. V  
provides power to the device and is also a monitored  
CC  
voltage. When V  
remains low for the reset timeout period after V  
drops below the selected threshold, RESET asserts low and  
CC  
C1  
C1  
V
CC  
rises above the threshold. Bypass  
CC  
V
to GND with a 0.1FF capacitor.  
CC  
C2  
B2  
C2  
GND  
Ground  
Active-Low Manual Reset Input 1. Internal 50kI pullup to V . Pull both MR1 and MR2  
CC  
MR1  
low for the setup delay (t ) to one-shot pulse RESET for the reset timeout period.  
SU  
Active-Low Manual Reset Input 2. Internal 50kI pullup to V . Pull the MR2 and MR1  
CC  
A2  
MR2  
low for the setup delay (t ) to one-shot pulse RESET for the reset timeout period.  
SU  
Resistor-Adjusted Setup Delay  
Detailed Description  
For the MAX16122–MAX16125 with the E setup delay  
suffix (MAX1612_WTE_+T), a resistor connected from  
SEL to GND sets the setup delay. Table 1b shows com-  
mon resistor values and the resulting setup delays. For  
resistor values not in the table, use the following formula  
to compute the setup delay:  
The MAX16122–MAX16125 low-current microprocessor  
reset circuits feature single or dual manual reset inputs  
with an extended setup period. The devices also feature  
an internal comparator to monitor 5V, 3.3V, 2.5V, and  
1.8V supplies.  
When the monitored supply voltage drops below the  
specified threshold, the active-low RESET output asserts  
R
20  
t
=
SU  
low and remains low for the reset timeout period (t ).  
RP  
The RESET output is one-shot pulse asserted for the  
reset timeout period. Supply voltage reset threshold is  
selectable through part suffix, see Table 3.  
where R is the resistor value in kI and t  
ing setup delay in seconds. For best results, use resistor  
is the result-  
SU  
values between 10kI and 500kI.  
Connect SEL to GND, V , or leave unconnected to  
CC  
select the different setup delays (depending on part suf-  
fix, see Table 1a), or connect to an external resistor to set  
the setup delays (E suffix only, see Table 1b).  
Reset Output  
The reset output is typically connected to the reset  
input of a microprocessor (FP). A FP’s reset input starts  
or restarts the FP in a known state. The MAX16122–  
MAX16125 FP supervisory circuits provide the reset  
logic to prevent code-execution errors during power-up,  
power-down, and brownout conditions (see the Typical  
Operating Circuits).  
The MAX16124/MAX16125 have one manual reset input  
(MR), one reset output (RESET), and one soft reset output  
(SRESET). The MAX16122/MAX16123 have two identical  
manual reset inputs (MR1 and MR2) and one reset output  
(RESET). A deglitch block is connected to each manual  
reset input to add a delay to the falling edge with a fixed  
The MAX16122/MAX16123 have a reset output RESET.  
The MAX16124/MAX16125 have a reset output RESET  
and a soft-reset output SRESET which is the debounced  
“mirror image” of MR (see Figure 1a).  
deglitch period of 20ms (t ).  
DB  
7

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