MA17501
Signal
I/O
Definition
AD00 - AD15
AS
CLKPC
CLK02
PAUSE
DS
HLDAK
HOLD
lN/OP
INTRE
lRDY
I/O
O/Z
O
O
External 16-Bit Address/Data Bus
Address Strobe Indicates Address lnformation on A/D Bus
Precharge Clock
Phase 2 Clock
l
DMA Acknowledge (A/D Bus to be used for DMA)
Data Strobe lndicates Data lnformation on A/D Bus
Hold Acknowledge
Hold Request Suspends lnternal Processor Functions
lnstruction/Operand lndicates Type of Memory Access
lnterrupt Enable
O/Z
O
l
O/Z
O
l
lnterrupt Unit Ready Signal
M/lO
M00 - M19
OSC
O/Z
l
l
Memory or lnput/Output lndicates Transaction on A/D Bus
20-Bit Microcode Bus
External Oscillator Clock
OVl
PlF
O
l
Overflow lndicator
Privileged Instruction Fault
RD/W
O/Z
Read/Write IndicatesData Direction on A/D Bus
RDY
l
l
O
O
O
I
Ready lnforms CPU of the Conclusion of External Bus Cycle
Reset Indicates Device Initialization
Interrupt Unit's Sync Clock
System Clock - CPU Sync Clock (External)
System Clock (Internal)
RESET
SYNCLK
SYNC
SYSCLK1
TEST
T1
Test Enable
Branch or Jump Control
O
VDD
Power (External), 5 Volts
GND
Ground
Table 1: Signal Definitions
2.4 DUAL-PORT REGISTER FILE
2.2 BARREL SHIFTER
The Register File is a dual port RAM structure containing
24, 16-bit registers. Sixteen of these registers are general
purpose and user accessible. These user accessible registers
- referred to as R0 through R15 - may be used as
accumulators, index registers, base registers temporary
operand registers, or stack pointers. The remaining eight
registers are only accessible by microcode.
The Barrel Shifter is a 32-bit input, 16-bit output right shift
network. A 32-bit operand may be shifted right arithmetically,
logically, or cyclically up to 31 bit positions in a single machine
cycle. While not directly accessible or visible to user programs,
the Barrel Shifter is utilized by microcode to effect all shift,
rotate, and normalize instructions with minimum execution
time.
Adjacent registers are concatenated to effectively form 32-
bit and 48-bit registers for storage of double precision and
extended-precision operands, respectively. Instructions
access these operands by specifying the register containing
the most significant part of the operand, and the register set
wraps around automatically under microcode control, e.g.,
R15 concatenates with R0 for 32-bit operands and R15
concatenates with R0 and R1 for 48-bit operands.
2.3 PARALLEL MULTIPLIER
The Parallel Multiplier performs a 4-bit multiplier by 24-bit
multiplicand multiplication plus accumulation in a single
machine cycle. Only four machine cycles are required to
complete a 16-bit by 16-bit multiplication. Contained within the
multiplier is a 48-bit product accumulation register with the
lower 24 bits serving as a source operand register.
On each multiply machine cycle, the lower four bits of the
accumulator are multiplied by 24 bits from the two ALU
operand source buses (R and S). The lower 24 bits of this 28-
bit product are then added to the upper 24 bits of the
accumulator and the whole accumulator is shifted right four
bits. This right shift makes room for the upper four bits of the
product. The four bits shifted out are used in the next multiply
iteration.
3
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