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M95080-VMN5 PDF预览

M95080-VMN5

更新时间： 2024-01-26 17:16:22
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管
页数 文件大小 规格书
21页 179K
描述
1KX8 SPI BUS SERIAL EEPROM, PDSO8, 0.150 INCH, PLASTIC, SO-8

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M95080-VMN5 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：8
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.51风险等级：5.66
JESD-30 代码：R-PDSO-G8长度：4.9 mm
内存密度：8192 bit内存集成电路类型：EEPROM
内存宽度：8功能数量：1
端子数量：8字数：1024 words
字数代码：1000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-20 °C
组织：1KX8封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE并行/串行：SERIAL
认证状态：Not Qualified座面最大高度：1.75 mm
串行总线类型：SPI最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：3.9 mmBase Number Matches：1

M95080-VMN5 数据手册

 浏览型号M95080-VMN5的Datasheet PDF文件第4页浏览型号M95080-VMN5的Datasheet PDF文件第5页浏览型号M95080-VMN5的Datasheet PDF文件第6页浏览型号M95080-VMN5的Datasheet PDF文件第8页浏览型号M95080-VMN5的Datasheet PDF文件第9页浏览型号M95080-VMN5的Datasheet PDF文件第10页 
M95640, M95320, M95160, M95080  
Table 6. Write Protected Block Size  
Status Register Bits  
Protected Block  
Array Addresses Protected  
BP1  
BP0  
M95640  
none  
M95320  
none  
M95160  
none  
M95080  
none  
0
0
1
1
0
1
0
1
none  
Upper quarter  
Upper half  
1800h - 1FFFh  
1000h - 1FFFh  
0000h - 1FFFh  
0C00h - 0FFFh  
0800h - 0FFFh  
0000h - 0FFFh  
0600h - 07FFh  
0400h - 07FFh  
0000h - 07FFh  
0300h - 03FFh  
0200h - 03FFh  
0000h - 03FFh  
Whole memory  
The initial delivery state of the BP1 and BP0 bits is  
00, indicating a write-protection size of 0.  
Software Protected Mode (SPM)  
register, are write-protected. The only way to re-  
enable writing new values to the status register is  
to pull the W pin high. This cause the device to  
leave the Hardware Protected Mode, and to revert  
to being in the Software Protected Mode. (The  
value in the BP1 and BP0 bits will not have been  
changed).  
The act of writing a non-zero value to the BP1 and  
BP0 bits causes the Software Protected Mode  
(SPM) to be started. All attempts to write a byte or  
page in the protected area are ignored, even if the  
Write Enable Latch is set. However, writing is still  
allowed in the unprotected area of the memory  
array and to the SRWD, BP1 and BP0 bits of the  
status register, provided that the WEL bit is first  
set.  
Further details of the operation of Write Protect  
(W) are given earlier, on page 3.  
Typical Use of HPM and SPM  
Write Protect (W) can be driven by an output port  
of a microcontroller. It is important that Write  
Protect (W) remains stable (permanently High, or  
permanently Low) throughout the duration of the  
Write Status Register sequence, shown in Figure  
7).  
Hardware Protected Mode (HPM)  
The Hardware Protected Mode (HPM) offers a  
higher level of protection, and can be selected by  
setting the SRWD bit after pulling down the W pin  
or by pulling down the W pin after setting the  
SRWD bit. The SRWD is set by the WSR  
instruction, provided that the WEL bit is first set.  
The setting of the SRWD bit can be made  
independently of, or at the same time as, writing a  
new value to the BP1 and BP0 bits.  
It is also possible to connect it permanently to V  
SS  
(by a solder connection, or through a pull-down  
resistor). The manufacturer of such a printed  
circuit board can take the memory device, still in its  
initial delivery state, and can solder it directly on to  
the board. After power on, the microcontroller can  
be instructed to write the protected data into the  
appropriate area of the memory. When it has  
finished, the appropriate values are written to the  
Once the device is in the Hardware Protected  
Mode, the data bytes in the protected area of the  
memory array, and the content of the status  
Figure 7. WRSR: Write Status Register Sequence  
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
STATUS REG.  
C
INSTRUCTION  
7
6
5
4
3
2
0
1
D
Q
MSB  
HIGH IMPEDANCE  
AI02282B  
7/21  
1...45678910...21

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