Datasheet > M82C288-10

M82C288-10

更新时间： 2024-02-21 20:20:18

品牌	Logo	应用领域
英特尔 - INTEL		控制器
页数	文件大小	规格书
20页	329K
描述
BUS CONTROLLER FOR M80286 PROCESSORS

阅读下载

获取价格

如果您发现信息不准确，欢迎纠错

M82C288-10 数据手册

M82C288

CMDLY is first sampled on the falling edge of the

CLK ending T . If sampled HIGH, the command out-

put is not activated, and CMDLY is again sampled

on the next falling edge of CLK. Once sampled

LOW, the proper command output becomes active

sitions of all signals in all modes. Instead, all signal

timing relationships are shown via the general cas-

es. Special cases are shown when needed. The

waveforms provide some functional descriptions of

the M82C288; however, most functional descriptions

are provided in Figures 5 through 11.

mand goes active no earlier than shown in Figures 9

immediately if MB

0. If MB

1, the proper com-

and 10.

To find the timing specification for a signal transition

in a particular mode, first look for a special case in

the waveforms. If no special case applies, then use

a timing specification for the same or related func-

tion in another mode.

READY can terminate a bus cycle before CMDLY

allows a command to be issued. In this case no

commands are issued an the bus controller will de-

activate DEN and DT/R in the same manner as if a

command has been issued.

Waveforms Discussion

The waveforms show the timing relationships of in-

puts and outputs and do not show all possible tran-

下载PDF

型号	品牌	描述	获取价格	数据表
M82C288-6	INTEL	BUS CONTROLLER FOR M80286 PROCESSORS	获取价格
M82C288-8	INTEL	BUS CONTROLLER FOR M80286 PROCESSORS	获取价格
M82C55A	OKI	CMOS PROGRAMMABLE PERIPHERAL INTERFACE	获取价格
M83	MITSUBISHI	SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER	获取价格
M83	TE	Triple-Balanced Mixer	获取价格
M83	MACOM	Triple Balanced	获取价格