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M81049P PDF预览

M81049P

更新时间: 2024-01-15 23:53:03
品牌 Logo 应用领域
三菱 - MITSUBISHI 触发器锁存器逻辑集成电路光电二极管驱动
页数 文件大小 规格书
8页 116K
描述
OCTAL D-TYPE FLIP-FLOP DRIVER WITH CLEAR

M81049P 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:SDIP, SDIP20,.3针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84系列:81049
JESD-30 代码:R-PDIP-T20长度:19 mm
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:20000000 Hz
位数:8功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SDIP封装等效代码:SDIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE, SHRINK PITCH
电源:5 V认证状态:Not Qualified
座面最大高度:4.5 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子形式:THROUGH-HOLE端子节距:1.778 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:20 MHz
Base Number Matches:1

M81049P 数据手册

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MITSUBISHI SEMICONDUCTOR <TRANSISTOR ARRAY>  
M81049P/SP/FP  
OCTAL D-TYPE FLIP-FLOP DRIVER WITH CLEAR  
DESCRIPTION  
PIN CONFIGURATION (TOP VIEW)  
M81049 is octal D-type flip-flop driver by 20-pin package. It  
has 8 same circuit units which is composed of D-type flip-flop  
logic circuit and high voltage NchMOS output transistor.  
M81049 has a common direct clear input and a common  
clock input.  
CLR  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VDD  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
Y8  
GND  
INPUT  
OUTPUT  
FEATURES  
Lineup with three packages  
High breakdown voltage (BVDSX 40V)  
Drain output current (IDS(max) = 200mA)  
With input protection diodes  
CLK 10  
Pin assignment of input-output flow through  
Wide operating temperature range (Ta = 40 to +85°C)  
Package type 20P4(P)  
20P4B(SP)  
20P2N(FP)  
APPLICATION  
LED drive  
FUNCTION  
The common direct clear input and common clock input are  
connected to every circuit unit by the same way. Signal at the  
D inputs is transferred to Y outputs by D-type flip-flops on the  
positive-going edge of the clock pulse.  
If CLR is set to “L”, outputs Y1-Y8 will be altogether set to “H”  
regardless of D1-D8 and CLK.  
The maximum drain current of an output is 200mA. The  
maximum between drain-source is 40V.  
LOGIC DIAGRAM (POSITIVE LOGIC)  
Y1  
19  
Y2  
18  
Y3  
17  
Y4  
16  
Y5  
15  
Y6  
14  
Y7  
13  
Y8  
12  
20  
11  
VDD  
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
CK  
CK  
CK  
CK  
CK  
CK  
CK  
CK  
10  
1
CLK  
CLR  
R
R
R
R
R
R
R
R
GND  
2
3
4
5
6
7
8
9
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
Jun. 2009  

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