Renesas LSIs
M6MGB/T641S8AKT
67,108,864-BIT (4,194,304-WORD BY 16-BIT / 8,388,608-WORD BY 8-BIT) CMOS
FLASH MEMORY &
8,388,608-BIT (524,288-WORD BY 16-BIT / 1,048,576-WORD BY 8BIT) CMOS SRAM
Stacked- mMCP (micro Multi Chip Package)
DESCRIPTION
The M6MGB/T641S8AKT is a Stacked micro Multi Chip
Package (S- m MCP) that contents 64M-bit Flash memory
and 8M-bit Static RAM and are available in a 52-pin TSOP
for lead free use.
The M6MGB/T641S8AKT is suitable for a high performance
cellular phone and a mobile PC that are required to be small
mounting area, weight and small power dissipation.
FEATURES
64M-bit Flash memory is a 4,194,304 words / 8,388,608
bytes single power supply and high performance non-
volatile memory fabricated by CMOS technology for the
peripheral circuit and DINOR IV (Divided bit-line NOR IV)
architecture for the memory cell. All memory blocks are
Access time
Flash
SRAM
70ns (Max.)
85ns (Max.)
Supply voltage
VCC = 2.7 ~ 3.0V
locked and can not be programmed or erased, when F-WP# Ambient temperature
is Low. Using Software Lock Release function, program or
erase operation can be executed.
Ta=-40 ~ 85 °C
Package
52pin TSOP(Type-II), Lead pitch 0.4mm
Outer-lead finishing : Sn-Cu
8M-bit SRAM is a 524,288 words / 1,048576 bytes
asynchronous SRAM fabricated by CMOS technology for
the peripheral circuit and CMOS type transistor for the
memory cell.
APPLICATION
Mobile communication products
PIN CONFIGURATION (TOP VIEW)
A15
A14
A13
A12
A11
A10
A9
A16
1
2
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
BYTE#
S-UB#
GND
S-LB#
DQ15/A-1
DQ7
3
4
5
6
7
A8
DQ14
DQ6
8
A19
9
DQ13
DQ5
S-CE1#
WE#
F-RP#
F-WP#
S-VCC
S-CE2
A21
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DQ12
DQ4
M6MGB/T641S8AKT
F-VCC
DQ11
DQ3
DQ10
DQ2
A20
A18
DQ9
A17
DQ1
A7
DQ8
A6
DQ0
A5
A4
OE#
GND
F-CE#
A0
A3
A2
A1
10.49 mm
Outline 52PTJ-A
F-VCC
S-VCC
GND
A-1-A18
A19-A21
DQ0-DQ15
F-CE#
S-CE#,S-CE2
OE#
:Vcc for Flash
:Vcc for SRAM
WE#
:Flash/SRAM Write Enable
:Flash Write Protect
:Flash Reset Power Down
:Flash/SRAM Byte Enable
:SRAM Lower Byte
F-WP#
F-RP#
BYTE#
S-LB#
S-UB#
:GND for Flash/SRAM
:Flash/SRAM common Address
:Address for Flash
:Data I/O
:Flash Chip Enable
:SRAM Chip Enable
:Flash/SRAM Output Enable
:SRAM Upper Byte
Rev.1.0_48a_bebz
1