MITSUBISHI LSIs
M6MGB/T166S4BWG
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
DESCRIPTION
FEATURES
The MITSUBISHI M6MGB/T166S4BWG is a Stacked Chip
Scale Package (S-CSP) that contents 16M-bits flash
memory and 4M-bits Static RAM in a 72-pin S-CSP.
• Access time
Flash Memory
SRAM
90ns (Max.)
85ns (Max.)
Vcc=2.7 ~ 3.6V
• Supply voltage
• Ambient temperature
W version
16M-bits Flash memory is a 1,048,576 words, 3.3V-only,
and high performance non-volatile memory fabricated by
CMOS technology for the peripheral circuit and
DINOR(DIvided bit-line NOR) architecture for the memory
cell.
Ta=-20 ~ 85°C
• Package : 72-pin S-CSP , 0.8mm ball pitch
4M-bits SRAM is a 262,144words unsynchronous SRAM
fabricated by silicon-gate CMOS technology.
APPLICATION
Mobile communication products
M6MGB/T166S4BWG is suitable for the application of the
mobile-communication-system to reduce both the mount
space and weight .
PIN CONFIGURATION (TOP VIEW)
INDEX
H
G
F
E
D
C
B
A
NC
NC
1
2
F-VCC
:Vcc for Flash
NC
DU
A5
NC
S-VCC
F-GND
GND
:Vcc for SRAM
:GND for Flash
GND
F-A18 S-LB#
F-A17 S-UB#
F-WE#
F-
F-WP#
A16 DU
A8 A11
A10 A15
A9 A14
3
:Flash/SRAM common GND
F-RP# RY/BY#
DU
4
A0-A16
:Flash/SRAM
common Address
F-A19
A7
S-OE#
DU DU
A4
5
:Address for Flash
:Address for SRAM
F-A17-F-A19
S-A17
DQ11
S-A17
A0
A6 DU
DU
6
DQ0-DQ15
:Flash/SRAM
common Data I/O
F-CE#
F-GND
F-OE#
DU
NC
NC
DQ12
DQ13
DQ15
A3
A13
DQ9 DU
7
F-CE#
S-CE1#
S-CE2
F-OE#
S-OE#
F-WE#
S-WE#
F-WP#
F-RP#
:Flash Chip Enable
:SRAM Chip Enable
:SRAM Chip Enable
S-
CE2
DQ10
S-WE#
A2 DQ8
DQ6
A12
8
S-VCC
F-VCC
DQ14
A1
F-GND
DQ0 DQ2
DQ1 DQ3
DQ4
9
:Flash Output Enable
:SRAM Output Enable
S-
CE1#
DU
NC
NC
DQ5 DQ7
10
11
12
:Flash Write Enable
:SRAM Write Enable
:Flash Write Protect
:Flash Reset Power Down
:Flash Ready /Busy
:SRAM Lower Byte
:SRAM Upper Byte
F-RY/BY#
S-LB#
S-UB#
8.0 mm
NC:Non Connection
DU:Don't Use (Note: Should be open)
1
Apr. 1999 , Rev.1.7