Datasheet > 存储 > SRAM> M5M5Y5672TG-22

M5M5Y5672TG-22

更新时间： 2024-01-05 09:25:45

品牌	Logo	应用领域
三菱 - MITSUBISHI		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
27页	241K
描述
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM

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技术参数
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M5M5Y5672TG-22 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
零件包装代码：	BGA	包装说明：	BGA, BGA209,11X19,40
针数：	209	Reach Compliance Code：	unknown
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.68	最长访问时间：	2.8 ns
其他特性：	PIPELINED ARCHITECTURE	最大时钟频率 (fCLK)：	225 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B209
JESD-609代码：	e0	长度：	22 mm
内存密度：	18874368 bit	内存集成电路类型：	STANDARD SRAM
内存宽度：	72	功能数量：	1
端子数量：	209	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256KX72	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA209,11X19,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY	并行/串行：	PARALLEL
电源：	1.8 V	认证状态：	Not Qualified
座面最大高度：	3.5 mm	最大待机电流：	0.02 A
最小待机电流：	1.7 V	子类别：	SRAMs
最大压摆率：	0.5 mA	最大供电电压 (Vsup)：	1.95 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	宽度：	14 mm
Base Number Matches：	1

M5M5Y5672TG-22 数据手册

MITSUBISHI LSIs

2001.May Rev.0.1

Advanced Information

Some parametric limits are subject to change.

M5M5Y5672TG – 25,22,20

Notice: This is not final specification.

18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM

Synchronous circuitry allows for precise cycle control triggered

by a positive edge clock transition.

DESCRIPTION

The M5M5Y5672TG is a family of 18M bit synchronous SRAMs

organized as 262144-words by 72-bit. It is designed to eliminate

dead bus cycles when turning the bus around between reads

and writes, or writes and reads. Mitsubishi's SRAMs are

fabricated with high performance, low power CMOS technology,

providing greater reliability. M5M5Y5672TG operates on a single

1.8V power supply and are 1.8V CMOS compatible.

Synchronous signals include : all Addresses, all Data Inputs,

all Chip Enables (E1#, E2, E3), Address Advance/Load (ADV),

Byte Write Enables (BWa#, BWb#, BWc#, BWd#, BWe#, BWf#,

BWg#, BWh#), Echo Clock outputs (CQ1, CQ1#, CQ2, CQ2#)

and Read/Write (W#). Write operations are controlled by the

eight Byte Write Enables (BWa# - BWh#) and Read/Write(W#)

inputs. All writes are conducted with on-chip synchronous

self-timed write circuitry.

The Echo Clocks are delayed copies of the RAM clock, CLK.

Echo Clocks are designed to track changes in output driver

delays due to variance in die temperature and supply voltage.

The ZQ pin supplied with selectable impedance drivers, allows

selection between nominal drive strength (ZQ LOW) for

multi-drop bus application and low drive strength (ZQ floating or

HIGH) point-to-point applications.

The sense of two User-Programmable Chip Enable inputs (E2,

E3), whether they function as active LOW or active HIGH inputs,

is determined by the state of the programming inputs, EP2 and

EP3.

The Linear Burst order (LBO#) is DC operated pin. LBO# pin

will allow the choice of either an interleaved burst, or a linear

burst.

FEATURES

• Fully registered inputs and outputs for pipelined operation

• Fast clock speed: 250, 225, and 200 MHz

• Fast access time: 2.6, 2.8, 3.2 ns

• Single 1.8V +150/-100mV power supply VDD

• Separate VDDQ for 1.8V I/O

• Individual byte write (BWa# - BWh#) controls may be tied

LOW

• Single Read/Write control pin (W#)

• Echo Clock outputs track data output drivers

• ZQ mode pin for user-selectable output drive strength

• 2 User programmable chip enable inputs for easy depth

expansion

• Linear or Interleaved Burst Modes

• JTAG boundary scan support

All read, write and deselect cycles are initiated by the ADV

Low input. Subsequent burst address can be internally

generated as controlled by the ADV HIGH input.

APPLICATION

High-end networking products that require high bandwidth, such

as switches and routers.

FUNCTION

PACKAGE

Bump

Body Size

14mm X 22mm

Bump Pitch

1mm

M5M5Y5672TG

209(11X19) bump BGA

PART NAME TABLE

Standby Current

(max.)

Active Current

Part Name

Frequency

Access

Cycle

(max.)

550mA

500mA

450mA

M5M5Y5672TG -25

M5M5Y5672TG -22

M5M5Y5672TG -20

250MHz

225MHz

200MHz

2.6ns

2.8ns

3.2ns

4.0ns

4.4ns

5.0ns

20mA

Advanced Information

M5M5Y5672TG REV.0.1

MITSUBISHI

ELECTRIC

12 3 4 5 6 7...27

中文翻译

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与M5M5Y5672TG-22相关器件

型号	品牌	获取价格	描述	数据表
M5M5Y5672TG-25	RENESAS	获取价格	18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
M5M5Y5672TG-25	MITSUBISHI	获取价格	18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
M5M5Y816WG-55HI/70HI/85HI	ETC	获取价格	Memory
M5M5Y816WG-70HI	MITSUBISHI	获取价格	8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
M5M5Y816WG-85HI	MITSUBISHI	获取价格	8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
M5M5-Z-M	MSYSTEM	获取价格	Super-mini Terminal Block Signal Conditioners M5-UNIT
M5M5-Z-M/A1	MSYSTEM	获取价格	Super-mini Terminal Block Signal Conditioners M5-UNIT
M5M5-Z-M/K	MSYSTEM	获取价格	Super-mini Terminal Block Signal Conditioners M5-UNIT
M5M5-Z-M/Q	MSYSTEM	获取价格	Super-mini Terminal Block Signal Conditioners M5-UNIT
M5M5-Z-R	MSYSTEM	获取价格	Super-mini Terminal Block Signal Conditioners M5-UNIT

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