'97.4.7
MITSUBISHI LSIs
M5M5256DP,KP,FP,VP,RV -45LL-W,-55LL-W,-70LL-W,
-45XL-W,-55XL-W,-70XL-W
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5256DP,KP,FP,VP,RV is
determined by a combination of the device control inputs /S,
/W and /OE. Each mode is summarized in the function table.
A write cycle is executed whenever the low level /W
overlaps with the low level /S. The address must be set up
before the write cycle and must be stable during the entire
cycle. The data is latched into a cell on the trailing edge of
/W, /S, whichever occurs first, requiring the set-up and hold
time relative to these edge to be maintained. The output
enable /OE directly controls the output stage. Setting the
/OE at a high level,the output stage is in a high-impedance
state, and the data bus contention problem in the write cycle
is eliminated.
A read cycle is executed by setting /W at a high level and
/OE at a low level while /S are in an active state.
When setting /S at a high level, the chip is in a
non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a
high-impedance state, allowing OR-tie with other chips and
memory expansion by /S. The power supply current is
reduced as low as the stand-by current which is specified
as Icc3 or Icc4, and the memory data can be held at +2V
power supply, enabling battery back-up operation during
power failure or power-down operation in the non-selected
mode.
FUNCTION TABLE
Mode
DQ
Icc
/S /W /OE
High-impedance
DIN
Stand-by
Active
H
X
X
Non selection
Write
L
L
L
L
X
L
Active
Read
DOUT
H
H
Active
H
High-impedance
BLOCK DIAGRAM
A 8
25
11
DQ1
DQ2
DQ3
32768 WORD
X 8BIT
A 13
A 14
26
1
12
13
2
2
A 12
A 7
15
16
DQ4
DQ5
DQ6
DATA I/O
3
4
5
6
7
(512 ROWS X
A 6
17
18
A 5
A 4
512 COLUMNS)
DQ7
DQ8
19
ADDRESS
INPUT
A 3
A 2
8
9
A 1
A 0
10
21
23
24
A 10
A 11
A 9
CLOCK
GENERATOR
WRITE CONTROL
INPUT /W
27
20
22
VCC
(5V)
28
CHIP SELECT
INPUT
/S
14 GND
(0V)
OUTPUT ENABLE
INPUT
/OE
MITSUBISHI
ELECTRIC
2