'97.4.7
MITSUBISHI LSIs
M5M5256DP,KP,FP,VP,RV -45LL-W,-55LL-W,-70LL-W,
-45XL-W,-55XL-W,-70XL-W
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Ta = -20~70°C, Vcc=5V±10%, unless otherwise noted )
(1) MEASUREMENT CONDITIONS
Input pulse level··················I·HV=2.4V,VIL=0.6V
Input rise and fall time··········5ns
Vcc
1.8kW
Reference level···················O·VH=VOL=1.5V
DQ
Output loads·························Fig.1,CL=30pF (-45LL,-45XL )
990W
CL
CL=50pF (-55LL,-55XL )
(Including
scope and JIG)
CL=100pF (-70LL,-70XL )
CL=5pF (for ten,tdis)
Transition is measured ±500mV from steady
Fig.1 Output load
state voltage. (for ten,tdis)
Parameter
(2) READ CYCLE
Limits
-55LL, XL
Unit
Symbol
-45LL, XL
-70LL, XL
Min Max Min Max Min Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCR
Read cycle time
Address access time
Chip select access time
Output enable access time
Output disable time after /S high
45
55
70
ta(A)
ta(S)
ta(OE)
tdis(S)
45
45
25
15
15
55
55
30
20
20
70
70
35
25
25
tdis(OE) Output disable time after /OE high
ten(S)
Output enable time after /S low
ten(OE) Output enable time after /OE low
tV(A) Data valid time after address
5
5
10
5
5
10
5
5
10
(3) WRITE CYCLE
Limits
-55LL, XL
Min Max Min Max Min Max
-45LL, XL
-70LL, XL
Symbol
Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
tw(W)
tsu(A)
tsu(A-WH)
tsu(S)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
45
35
0
55
40
0
70
50
0
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to /W high
Chip select setup time
Data setup time
Data hold time
Write recovery time
Output disable time from /W low
Output disable time from /OE high
Output enable time from /W high
Output enable time from /OE low
40
40
20
0
50
50
25
0
65
65
30
0
0
0
0
15
15
20
20
25
25
5
5
5
5
5
5
MITSUBISHI
ELECTRIC
4