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M5M5256DVP-85VXL-W PDF预览

M5M5256DVP-85VXL-W

更新时间: 2024-01-15 01:11:34
品牌 Logo 应用领域
三菱 - MITSUBISHI /
页数 文件大小 规格书
7页 50K
描述
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM

M5M5256DVP-85VXL-W 技术参数

生命周期:Obsolete零件包装代码:TSOP
包装说明:SOP,针数:28
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.75
最长访问时间:85 nsJESD-30 代码:R-PDSO-G28
内存密度:262144 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端口数量:1端子数量:28
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32KX8
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL认证状态:Not Qualified
最小待机电流:2 V最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:MIXMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子位置:DUALBase Number Matches:1

M5M5256DVP-85VXL-W 数据手册

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'97.4.7  
MITSUBISHI LSIs  
M5M5256DFP,VP,RV -70VLL-W,-85VLL-W,  
-70VXL-W,-85VXL-W  
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM  
FUNCTION  
The operation mode of the M5M5256DP,KP,FP,VP,RV is  
determined by a combination of the device control inputs /S,  
/W and /OE. Each mode is summarized in the function table.  
A write cycle is executed whenever the low level /W  
overlaps with the low level /S. The address must be set up  
before the write cycle and must be stable during the entire  
cycle. The data is latched into a cell on the trailing edge of  
/W, /S, whichever occurs first, requiring the set-up and hold  
time relative to these edge to be maintained. The output  
enable /OE directly controls the output stage. Setting the  
/OE at a high level,the output stage is in a high-impedance  
state, and the data bus contention problem in the write cycle  
is eliminated.  
A read cycle is executed by setting /W at a high level and  
/OE at a low level while /S are in an active state.  
When setting /S at a high level, the chip is in a  
non-selectable mode in which both reading and writing are  
disabled. In this mode, the output stage is in a  
high-impedance state, allowing OR-tie with other chips and  
memory expansion by /S. The power supply current is  
reduced as low as the stand-by current which is specified  
as Icc3 or Icc4, and the memory data can be held at +2V  
power supply, enabling battery back-up operation during  
power failure or power-down operation in the non-selected  
mode.  
FUNCTION TABLE  
Mode  
DQ  
Icc  
/S /W /OE  
High-impedance  
DIN  
Stand-by  
Active  
H
X
X
Non selection  
Write  
L
L
L
L
X
L
Active  
Read  
DOUT  
H
H
Active  
H
High-impedance  
BLOCK DIAGRAM  
A 8  
25  
11  
DQ1  
DQ2  
DQ3  
32768 WORD  
X 8BIT  
A 13  
A 14  
26  
1
12  
13  
2
A 12  
A 7  
15  
16  
DQ4  
DQ5  
DQ6  
DATA I/O  
3
4
5
6
7
(512 ROWS X  
A 6  
17  
18  
A 5  
A 4  
512 COLUMNS)  
DQ7  
DQ8  
19  
ADDRESS  
INPUT  
A 3  
A 2  
8
9
A 1  
A 0  
10  
21  
23  
24  
A 10  
A 11  
A 9  
CLOCK  
GENERATOR  
WRITE CONTROL  
INPUT /W  
27  
20  
22  
VCC  
(3.3V)  
28  
CHIP SELECT  
INPUT  
/S  
14 GND  
(0V)  
OUTPUT ENABLE  
INPUT  
/OE  
MITSUBISHI  
ELECTRIC  
2

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