MITSUBISHI LSIs
M5M29KB/T800AVP
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 5.0V-ONLY, BLOCK ERASE FLASH MEMORY
BLOCK DIAGRAM
128 WORD PAGE BUFFER
A18
Main Block
32KW
A17
A16
VCC (5.0V)
GND (0V)
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
15
X-DECODER
Main Block
32KW
Parameter Block6
Parameter Block5
Parameter Block4
Parameter Block3
Parameter Block2
Parameter Block1
4KW
4KW
4KW
4KW
4KW
4KW
ADDRESS
INPUTS
Boot Block
8KW
A4
A3
A2
A1
A0
Y-GATE / SENSE AMP.
MULTIPLEXER
Y-DECODER
STATUS / ID REGISTER
CHIP ENABLE INPUT
CE#
OUTPUT ENABLE INPUT OE#
WRITE ENABLE INPUT WE#
WRITE PROTECT INPUT WP1#
CUI
WSM
INPUT/OUTPUT
BUFFERS
RESET/POWER DOWN INPUT RP#
BYTE ENABLE INPUT
BYTE#
READY/BUSY OUTPUT RY/BY#
DQ15/A-1DQ14DQ13DQ12
DQ3DQ2DQ1DQ0
DATA INPUTS/OUTPUTS
FUNCTION
Alternating Background Operation (BGO)
The M5M29KB/T800AVP allows to read array from one bank
while the other bank operates in software command write
cycling or the erasing / programming operation in the
background. Read array operation with the other bank in
BGO is performed by changing the bank address without
any additional command. When the bank address points the
The M5M29KB/T800AVP includes on-chip program/erase control
circuitry. The Write State Machine (WSM) controls block erase
and byte/page program operations. Operational modes are
selected by the commands written to the Command User Interface
(CUI). The Status Register indicates the status of the WSM and
when the WSM successfully completes the desired program or
block erase operation.
bank in the erasing
/
programming operation, the
data is read out from the status register. The
access time with BGO is the same as the normal
read operation.
A Deep Powerdown mode is enabled when the RP# pin is at GND,
minimizing power consumption.
Read
The M5M29KB/T800AVP has three read modes, which accesses
to the memory array, the Device Identifier and the Status Register.
The appropriate read command are required to be written to the
Output Disable
When OE# is at VIH, output from the devices is disabled.
Data input/output are in a high-impedance(High-Z) state.
CUI.
Upon initial device powerup or after exit from deep
Standby
powerdown, the M5M29KB/T800AVP automatically resets to read
array mode. In the read array mode, low level input to CE# and
OE#, high level input to WE# and RP#, and address signals to the
address inputs (A0-A18:Word mode, A-1, A0-A18:Byte mode)
output the data of the addressed location to the data input/output
(D0-D15:Word mode, D0-D7:Byte mode).
When CE# is at VIH, the device is in the standby mode and its
power consumption is reduced. Data input/output are in a
high-impedance(High-Z) state. If the memory is deselected
during block erase or program, the internal control circuits
remain active and the device consume normal active power
until the operation completes.
Write
Deep Power-Down
Writes to the CUI enables reading of memory array data, device
identifiers and reading and clearing of the Status Register. They
also enable block erase and program. The CUI is written by
bringing WE# to low level, while CE# is at low level and OE# is at
high level. Address and data are latched on the earlier rising edge
of WE# and CE#. Standard micro-processor write timings are
used.
When RP# is at VIL, the device is in the deep powerdown
mode and its power consumption is substantially low. During
read modes, the memory is deselected and the data
input/output are in a high-impedance(High-Z) state. After
return from powerdown, the CUI is reset to Read Array , and
the Status Register is cleared to value 80H.
During block erase or program modes, RP# low will abort
either operation. Memory array data of the block being altered
become invalid.
June 1998 , Rev.3.1
2
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