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M54HC192M1R PDF预览

M54HC192M1R

更新时间: 2024-09-30 22:54:07
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意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
15页 313K
描述
SYNCHRONOUS UP/DOWN DECADE(,BINARY) COUNTER

M54HC192M1R 数据手册

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M54/M74HC192  
M54/M74HC193  
HC192 - SYNCHRONOUS UP/DOWN DECADE COUNTER  
HC193 - SYNCHRONOUS UP/DOWN BINARY COUNTER  
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HIGH SPEED  
fMAX = 54 MHz (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE WITH  
54/74LS192-193  
ORDER CODES :  
M54HCXXXF1R  
M74HCXXXB1R  
M74HCXXXM1R  
M74HCXXXC1R  
DESCRIPTION  
The M54/74HC192/193 are ahigh speed CMOSSYN-  
CHRONOUS UP/DOWN DECADE COUNTERS fab-  
ricated in silicon gate C2MOS technology. They have  
the same high speed performance of LSTTL combined  
with true CMOS low power consumption. The counter  
has two separate clock inputs, an UP COUNT input  
and a DOWN COUNT input. All outputs of the flip-flop  
are simultaneously triggered on the low to high transi-  
tion of either clock while the other input isheld high. The  
direction of counting is determined by which input is  
clocked. This counter may be preset by entering the  
desired data on the DATA A, DATA B, DATA C, and  
DATA D input. When the LOAD input is taken low the  
data is loaded independently of either clock input. This  
feature allows the counters to be used as divide-by-n  
counters by modifying the count length with the preset  
inputs. In addition the counter can also be cleared. This  
is accomplished by inputting a high on the CLEAR  
input. All 4 internal stages are set to low independently  
of either COUNT input. Both a BORROW and CARRY  
output areprovided toenable cascadingof bothupand  
down counting functions. The BORROW output pro-  
ducesa negative going pulse when thecounter under-  
flows and the CARRY outputs a pulse when the  
counter overflows. The counter can be cascaded by  
connecting the CARRY and BORROW outputs of one  
device to the COUNT UP and COUNT DOWN inputs,  
respectively, of the next device. All inputs are equipped  
with protection circuits against static discharge and  
transient excess voltage.  
PIN CONNECTIONS (top view)  
NC =  
No Internal  
Connection  
October 1992  
1/15  

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