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M54HC193DT PDF预览

M54HC193DT

更新时间: 2024-10-01 13:10:07
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意法半导体 - STMICROELECTRONICS 计数器
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13页 349K
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M54HC193DT 数据手册

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M54HC193  
RAD-HARD SYNCHRONOUS UP/DOWN BINARY COUNTER  
HIGH SPEED: f  
=55MHz (TYP.) at V =6V  
MAX CC  
LOW POWER DISSIPATION:  
=4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
V
NIH  
NIL  
CC  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
DILC-16  
FPC-16  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
FM  
EM  
V
CC  
DILC  
FPC  
M54HC193D  
M54HC193K  
M54HC193D1  
M54HC193K1  
PIN AND FUNCTION COMPATIBLE WITH  
54 SERIES 193  
SPACE GRADE-1: ESA SCC QUALIFIED  
50 krad QUALIFIED, 100 krad AVAILABLE ON  
REQUEST  
NO SEL UNDER HIGH LET HEAVY IONS  
IRRADIATION  
C, and DATA D input. When the LOAD input is  
taken low the data is loaded independently of  
either clock input. This feature allows the counters  
to be used as divide-by-n counters by modifying  
the count length with the preset inputs. In addition  
the counter can also be cleared. This is  
accomplished by inputting a high on the clear  
input. All 4 internal stages are set to low  
independently of either COUNT input. Both a  
BORROW and CARRY output are provided to  
enable cascading of both up and down counting  
functions. The BORROW output produces a  
negative going pulse when the counter underflows  
and the CARRY outputs a pulse when the  
counters overflows. The counter can be cascaded  
by connection the CARRY and BORROW outputs  
of one device to the COUNT UP and COUNT  
DOWN inputs, respectively, of the next device.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
DEVICE FULLY COMPLIANT WITH  
SCC-9204-065  
DESCRIPTION  
The M54HC193 is an high speed CMOS  
SYNCRONOUS  
COUNTERS fabricated with silicon gate C MOS  
technology.  
The counter has two separate clock inputs, an UP  
COUNT input and a DOWN COUNT input. All  
outputs of the flip-flop are simultaneously  
triggered on the low to high transition of either  
clock while the other input is held high. The  
direction of counting is determined by which input  
is clocked. This counter may be preset by entering  
the desired data on the DATA A, DATA B, DATA  
UP/DOWN  
BINARY  
2
PIN CONNECTION  
April 2004  
1/13  

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