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M471B6474DZ1-CG8 PDF预览

M471B6474DZ1-CG8

更新时间: 2024-02-01 06:24:28
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
31页 523K
描述
DDR DRAM Module, 64MX64, CMOS, ROHS COMPLIANT, SO-DIMM-204

M471B6474DZ1-CG8 技术参数

生命周期:Obsolete零件包装代码:DMA
包装说明:DIMM,针数:204
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.36风险等级:5.84
访问模式:SINGLE BANK PAGE BURST其他特性:SELF CONTAINED REFRESH
JESD-30 代码:R-XDMA-N204内存密度:4294967296 bit
内存集成电路类型:DDR DRAM MODULE内存宽度:64
功能数量:1端口数量:1
端子数量:204字数:67108864 words
字数代码:64000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:
组织:64MX64封装主体材料:UNSPECIFIED
封装代码:DIMM封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY认证状态:Not Qualified
自我刷新:YES最大供电电压 (Vsup):1.575 V
最小供电电压 (Vsup):1.425 V标称供电电压 (Vsup):1.5 V
表面贴装:NO技术:CMOS
温度等级:OTHER端子形式:NO LEAD
端子位置:DUALBase Number Matches:1

M471B6474DZ1-CG8 数据手册

 浏览型号M471B6474DZ1-CG8的Datasheet PDF文件第1页浏览型号M471B6474DZ1-CG8的Datasheet PDF文件第3页浏览型号M471B6474DZ1-CG8的Datasheet PDF文件第4页浏览型号M471B6474DZ1-CG8的Datasheet PDF文件第5页浏览型号M471B6474DZ1-CG8的Datasheet PDF文件第6页浏览型号M471B6474DZ1-CG8的Datasheet PDF文件第7页 
Unbuffered SoDIMM  
DDR3 SDRAM  
Table Contents  
1.0 DDR3 Unbuffered SoDIMM Ordering Information ......................................................................4  
2.0 Key Features .................................................................................................................................4  
3.0 Address Configuration .................................................................................................................4  
4.0 x64 DIMM Pin Configurations (Front side/Back side) ...............................................................5  
5.0 Pin Description .............................................................................................................................6  
6.0 ON DIMM Thermal Sensor ............................................................................................................6  
7.0 Input/Output Functional Description ..........................................................................................7  
8.0 Functional Block Diagram: .......................................................................................................... 8  
8.1 512MB, 64Mx64 Module(Populated as 1 rank of x16 DDR3 SDRAMs) ..................................................8  
8.2 1GB, 128Mx64 Module(Populated as 2 rank of x16 DDR3 SDRAMs).................................................... 9  
8.3 2GB, 256Mx64 Module(Populated as 2 rank of x8 DDR3 SDRAMs) ....................................................10  
9.0 Absolute Maximum Ratings .......................................................................................................11  
9.1 Absolute Maximum DC Ratings ...................................................................................................11  
9.2 DRAM Component Operating Temperature Range .........................................................................11  
10.0 AC & DC Operating Conditions ...............................................................................................11  
10.1 Recommended DC Operating Conditions (SSTL - 15) ..................................................................11  
11.0 AC & DC Input Measurement Levels .......................................................................................12  
11.1 AC and DC Logic input levels for single-ended signals ...............................................................12  
11.2 Differential swing requirement for differntial signals ..................................................................13  
11.2.1 Single-ended requirements for differential signals ..............................................................14  
11.3 AC and DC logic input levels for Differential Signals ...................................................................15  
11.4 Differential Input Cross Point Voltage .......................................................................................15  
11.5 Slew rate definition for Single Ended Input Signals .....................................................................16  
11.5.1 Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS) ...................................16  
11.5.2 Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH) ......................................16  
11.6 Slew rate definition for Differential Input Signals ........................................................................16  
12.0 AC and DC Output Measurement Levels ................................................................................17  
12.1 Single Ended AC and DC Output Levels ....................................................................................17  
12.2 Differential AC and DC Output Levels .......................................................................................17  
12.3.Single Ended Output Slew Rate ................................................................................................18  
12.4 Differential Output Slew Rate ...................................................................................................18  
13.0 IDD specification........................................................................................................................19  
13.1 IDD specification ....................................................................................................................20  
14.0 Input/Output Capacitance ........................................................................................................21  
14.1. 1Rx16 512MB SoDIMM ............................................................................................................21  
14.2. 2Rx16 1GB SoDIMM ...............................................................................................................21  
14.3. 2Rx8 2GB SoDIMM .................................................................................................................21  
15.0 Electrical Characteristics and AC timing ...............................................................................22  
15.1 Refresh Parameters by Device Density ......................................................................................22  
15.2 DDR3 SDRAM tRCD, tRP and tRC .............................................................................................22  
15.3 Timing parameters for DDR3-800, DDR3-1066 and DDR3-1333 ......................................................24  
16.0 Physical Dimensions : .............................................................................................................29  
16.1 64Mbx16 based 64Mx64 Module(1 Rank) ...................................................................................29  
16.2 64Mbx16 based 128Mx64 Module(2 Ranks) ...............................................................................30  
16.3 128Mbx8 based 256Mx64 Module(2 Ranks) ...............................................................................31  
2 of 31  
Rev. 0.5 November 2007  

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