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M41T315Y-65MH6F PDF预览

M41T315Y-65MH6F

更新时间: 2024-02-15 21:00:31
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计时器或实时时钟微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
24页 407K
描述
Serial Access Phantom RTC Supervisor

M41T315Y-65MH6F 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP28,.5
针数:28Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.92最大时钟频率:0.032 MHz
信息访问方法:SERIAL, 2-WIRE/I2C中断能力:N
JESD-30 代码:R-PDSO-G28JESD-609代码:e0
长度:18.1 mm端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP28,.5封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:3.05 mm子类别:Timer or RTC
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
最短时间:1/100 SECOND处于峰值回流温度下的最长时间:NOT SPECIFIED
易失性:NO宽度:8.56 mm
uPs/uCs/外围集成电路类型:TIMER, REAL TIME CLOCKBase Number Matches:1

M41T315Y-65MH6F 数据手册

 浏览型号M41T315Y-65MH6F的Datasheet PDF文件第4页浏览型号M41T315Y-65MH6F的Datasheet PDF文件第5页浏览型号M41T315Y-65MH6F的Datasheet PDF文件第6页浏览型号M41T315Y-65MH6F的Datasheet PDF文件第8页浏览型号M41T315Y-65MH6F的Datasheet PDF文件第9页浏览型号M41T315Y-65MH6F的Datasheet PDF文件第10页 
M41T315Y*, M41T315V, M41T315W  
OPERATION  
Figure 6., page 5 illustrates the main elements of  
the device. The following paragraphs describe the  
signals and functions.  
ister. If a match is found, the pointer increments to  
the next location of the comparison register and  
awaits the next WRITE cycle.  
Communication with the clock is established by  
pattern recognition of a serial bit stream of 64 bits  
which must be matched by executing 64 consecu-  
tive WRITE cycles containing the proper data on  
data in (D). All accesses which occur prior to rec-  
ognition of the 64-bit pattern are directed to mem-  
ory via the chip enable output pin (CEO).  
After recognition is established, the next 64 READ  
or WRITE Cycles either extract or update data in  
the clock and CEO remains high during this time,  
disabling the connected memory (see Table  
2., page 7).  
Data transfer to and from the timekeeping function  
is accomplished with a serial bit stream under con-  
trol of chip enable input (CEI), output enable (OE),  
and WRITE enable (WE). Initially, a READ cycle  
using the CEI and OE control of the clock starts the  
pattern recognition sequence by moving the point-  
er to the first bit of the 64-bit comparison register.  
Next, 64 consecutive WRITE cycles are executed  
using the CEI and WE control of the clock. These  
64 WRITE cycles are used only to gain access to  
the clock.  
If a match is not found, the pointer does not ad-  
vance and all subsequent WRITE cycles are ig-  
nored. If a READ cycle occurs at any time during  
pattern recognition, the present sequence is abort-  
ed and the comparison register pointer is reset.  
Pattern recognition continues for a total of 64  
WRITE cycles as described above until all the bits  
in the comparison register have been matched  
(see Figure 10., page 11.)  
With a correct match for 64 bits, access to the reg-  
isters is enabled and data transfer to or from the  
timekeeping registers may proceed. The next 64  
cycles will cause the device to either receive data  
on D, or transmit data on Q, depending on the lev-  
el of OE pin or the WE pin. Cycles to other locations  
outside the memory block can be interleaved with  
CEI cycles without interrupting the pattern recogni-  
tion sequence or data transfer sequence to the de-  
vice.  
For a SO16 pin package, a standard 32.768 kHz  
quartz crystal can be directly connected to the  
M41T315Y/V/W via pins 1 and 2 (XI, XO). The  
crystal selected for use should have a specified  
load capacitance (CL) of 12.5 pF (see Table  
10., page 17).  
When the first WRITE cycle is executed, it is com-  
pared to the first bit of the 64-bit comparison reg-  
Table 2. Operating Modes  
V
Mode  
Deselect  
WRITE  
READ  
CEI  
OE  
X
WE  
D
Q
Power  
Standby  
Active  
CC  
V
X
Hi-Z  
Hi-Z  
Hi-Z  
IH  
4.5 to 5.5V  
or  
3.0 to 3.6V  
or  
V
V
D
X
IL  
IL  
IN  
V
V
IL  
V
D
OUT  
Hi-Z  
Hi-Z  
Hi-Z  
Active  
IL  
IH  
2.7 to 3.3V  
V
V
IH  
V
READ  
Hi-Z  
Active  
IL  
IH  
(1)  
Deselect  
X
X
X
X
X
X
Hi-Z  
Hi-Z  
CMOS Standby  
V
to V  
(min)  
PFD  
SO  
(1)  
SO  
Deselect  
Hi-Z  
Battery Back-up Mode  
V  
Note: X = V or V ; V = Battery Back-up Switchover Voltage.  
IH  
IL  
SO  
Note: 1. See Table 11., page 17 for details.  
7/24  

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