Datasheet > M36W108AT100ZN5

M36W108AT100ZN5

更新时间： 2024-11-20 07:59:15

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
36页	252K
描述
Memory Circuit, 1MX8, CMOS, PBGA48, LGA-48

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数据手册

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M36W108AT100ZN5 数据手册

M36W108AT

M36W108AB

8 Mbit (1Mb x8, Boot Block) Flash Memory and

1 Mbit (128Kb x8) SRAM Low Voltage Multi-Memory Product

PRELIMINARY DATA

■ SUPPLY VOLTAGE

– V

= V

= 2.7V to 3.6V: for Program,

CCS

CCF

Erase and Read

■ ACCESS TIME: 100ns

■ LOW POWER CONSUMPTION

– Read: 40mA max. (SRAM chip)

– Stand-by: 30µA max. (SRAM chip)

– Read: 10mA max. (Flash chip)

– Stand-by: 100µA max. (Flash chip)

BGA

LGA

LBGA48 (ZM)

6 x 8 solder balls

LGA48 (ZN)

6 x 8 solder lands

FLASH MEMORY

■ 8 Mbit (1Mb x 8) BOOT BLOCK ERASE

■ PROGRAMMING TIME: 10µs typical

■ PROGRAM/ERASE CONTROLLER (P/E.C.)

– Program Byte-by-Byte

Figure 1. Logic Diagram

– Status Register bits and Ready/Busy Output

■ SECURITY PROTECTION MEMORY AREA

■ INSTRUCTION ADDRESS CODING: 3 digits

■ MEMORY BLOCKS

CCF CCS

– Boot Block (Top or Bottom location)

– Parameter and Main Blocks

A0-A19

DQ0-DQ7

■ BLOCK, MULTI-BLOCK and CHIP ERASE

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

M36W108AT

M36W108AB

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

E1S

E2S

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Device Code, M36W108AT: D2h

– Device Code, M36W108AB: DCh

SRAM

■ 1 Mbit (128Kb x 8)

AI02620

■ POWER DOWN FEATURES USING TWO

CHIP ENABLE INPUTS

■ LOW V

DATA RETENTION: 2V

March 1999

1/36

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

12 3 4 5 6 7...36

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