Datasheet > M1034-16-167.3280

M1034-16-167.3280

更新时间： 2024-02-21 19:56:41

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
14页	200K
描述
PLL Based Clock Driver, 1034 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC, LCC-36

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M1034-16-167.3280 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	9 X 9 MM, CERAMIC, LCC-36	针数：	36
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.84	系列：	1034
输入调节：	DIFFERENTIAL	JESD-30 代码：	S-CQCC-N36
JESD-609代码：	e3	长度：	8.99 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	功能数量：	1
反相输出次数：		端子数量：	36
实输出次数：	1	最高工作温度：	70 °C
最低工作温度：		输出特性：	3-STATE
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	QCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	3.1 mm	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子面层：	MATTE TIN	端子形式：	NO LEAD
端子节距：	0.635 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	8.99 mm
最小 fmax：	175 MHz	Base Number Matches：	1

M1034-16-167.3280 数据手册

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M1033/34

Integrated

Circuit

Systems, Inc.

VCSO BASED

LOCK PLL WITH

UTO WITCH

P r e l i m i n a r y I n f o r m a t i o n

indicates the reference selection status and the LOR

output always indicated the selected input reference

clock status. A successful automatic reselection is

indicated by a change of state of the REF_ACK output.

Using the AutoSwitch Feature

See also Table 6, Example AutoSwitch Sequence.

In application, the system must be powered up with the

device in Manual Select mode (AUTO pin is set low).

The activity monitor output (LOR) should then be polled

to verify that the input clock reference is valid.

If an automatic reselection is made to a non-active

reference clock input, the REF_ACK output will

change state and both LOR outputs will remain high.

REF_SEL should be set to select the desired input

clock reference. This selection determines the

No further automatic reselection is made by the device;

only one reselection is made each time the AutoSwitch

mode is armed by the system. AutoSwitch mode is

re-armed by the system by placing the device into

Manual Select mode (AUTO pin low) and then into

AutoSwitch mode again (AUTO pin high). Following an

automatic reselection and prior to selecting Manual

Select mode (AUTO pin low), the REF_SEL pin has no

control of reference selection. To prevent an

unintentional reference reselection, AutoSwitch mode

must not be re-enabled until the desired state of the

REF_SEL pin is set and the LOR output is low. It is

recommended to delay the re-arming of AutoSwitch

mode, following an automatic reselection, to ensure the

PLL is fully locked on the new reference.

reference clock to be used in Manual Select mode and

the initial reference clock used in AutoSwitch mode.

Sufficient time must be allocated for the PLL to acquire

lock to the selected input reference. In most system

configurations, where loop bandwidth is in the range of

100-1000 Hz and damping factor below 10, a delay of

500 ms should be sufficient. The REF_SEL input state

must be maintained when switching to AutoSwitch

mode (AUTO pin high) and in addition must still be

maintained until a reference fault occurs. If a reference

fault occurs on the selected reference input, the LOR

output goes high and the input reference is

automatically reselected. The REF_ACK output always

Example AutoSwitch Sequence

0 = Low; 1 = High. Example with REF_SEL initially set to 0 (i.e., DIF_REF0 selected)

Selected

REF_SEL

Input

REF_ACK AUTO LOR

Conditions

Output

Input Output

Clock Input

Initialization

Device power-up. Manual Select mode. DIF_REF0 input selected as the working reference.

Both input references should be active.

DIF_REF0

AUTO set to 1: Device placed in AutoSwitch mode (with DIF_REF0 as working reference

clock).

-1-

Operation & Activation

Normal operation with AutoSwitch mode armed, with DIF_REF0 as the working reference

clock; DIF_REF1 is the protection reference clock. Both input references should be active.

DIF_REF0

Due to loss of reference at DIF_REF0 input (clock fault), the LOR output asserts high, then

device immediately goes to the following stage below.

DIF_REF0

-1-

-DIF_REF1-

-1-

-0-

Device initiates an automatic reselection to DIF_REF1 (indicated by REF_ACK pin), and then

the LOR output asserts low, indicating an active reference on DIF_REF1.

Re-initialization

When operation of DIF_REF0 is restored, the device can be prepared once again for

AutoSwitch. Preparation begins by setting the REF_SEL pin to 1, which will maintain the

current reference input selection when entering Manual Select mode.

-1-

-0-

DIF_REF1

AUTO set to 0: Manual Select mode entered briefly, manually selecting DIF_REF1 as the

working reference.

-0-

-1-

DIF_REF1

AUTO set to 1: Device is now placed in AutoSwitch mode, re-initializing AutoSwitch with

DIF_REF1 now specified as the working reference clock.

Table 6: Example AutoSwitch Sequence

M1033/34 Preliminary Information 0.1

7 of 14

Revised 07Apr2005

Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400

1...4 5 678 9 10...14

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与M1034-16-167.3280相关器件

型号	品牌	描述	获取价格	数据表
M1034-16-167.3280LF	IDT	PLL Based Clock Driver, 1034 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9	获取价格
M1034-16-167.3316LF	IDT	PLL Based Clock Driver, 1034 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9	获取价格
M1034-16-167.7097LF	IDT	PLL Based Clock Driver, 1034 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9	获取价格
M1034-16-168.0400	IDT	PLL Based Clock Driver, 1034 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9	获取价格
M1034-16-168.0400LF	IDT	PLL Based Clock Driver, 1034 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9	获取价格
M1034-16-172.6423LF	IDT	PLL Based Clock Driver, 1034 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9	获取价格

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