Contents
14 Flash Dual-Operation Considerations ..........................................................................89
14.1 Flash Partitioning................................................................................................................89
14.2 Flash Read-While-Write Command Sequences.................................................................89
14.2.1 Simultaneous Flash Operation Details...................................................................90
14.2.2 Flash Write to Flash Asynchronous Read Transition.............................................90
14.2.3 Flash Write to Flash Synchronous Read Operation Transition..............................90
14.2.4 Flash Write with Clock Active.................................................................................90
14.2.5 Flash Read During Flash Buffered Programming..................................................91
14.3 Simultaneous Flash Operation Restrictions........................................................................91
15 Special Flash Read States.................................................................................................93
15.1 Flash Read Status Register................................................................................................93
15.1.1 Flash Clear Status Register...................................................................................94
15.2 Flash Read Device Identifier...............................................................................................95
15.3 CFI Query ...........................................................................................................................96
Part 3: LPSDRAM Operations ............................................................... 97
16 LSDRAM Register Definition.............................................................................................99
16.1 Mode Register ....................................................................................................................99
16.2 LPSDRAM Extended Mode Register................................................................................100
17 LPSDRAM Command and Operation...........................................................................101
17.1 LPSDRAM No Operation / LPSDRAM Deselect...............................................................101
17.2 LPSDRAM Active..............................................................................................................101
17.3 LPSDRAM Read Command .............................................................................................101
17.4 LPSDRAM Write Command .............................................................................................102
17.5 LPSDRAM Power-Down...................................................................................................102
17.6 LPSDRAM Deep Power-Down .........................................................................................103
17.7 LPSDRAM Clock Suspend ...............................................................................................103
17.8 LPSDRAM Precharge.......................................................................................................103
17.9 LPSDRAM Auto Precharge ..............................................................................................103
17.10 LPSDRAM Concurrent Auto Precharge............................................................................103
17.11 LPSDRAM Burst Terminate..............................................................................................110
17.12 LPSDRAM Auto Refresh ..................................................................................................110
17.13 LPSDRAM Self Refresh....................................................................................................111
Appendix A Flash Flowcharts.................................................................................................113
Appendix B Common Flash Interface..................................................................................121
Appendix C Intel® PXA27x Processor Memory Subsystem RAM Type ID...........133
Appendix D Additional Information ......................................................................................135
Appendix E Ordering Introduction........................................................................................137
Datasheet
Intel® PXA27x Processor Family Memory Subsystem
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