LTM8048
PIN FUNCTIONS
–
V
(Bank 1): V
and V comprise the isolated
BYP (Pin B2): The BYP pin is used to bypass the refer-
OUT1
OUT1
OUT
output of the LTM8048 flyback stage. Apply an external
ence of the LDO to achieve low noise performance from
–
–
capacitor between V
to exceed V
and V
. Do not allow V
the linear post regulator. The BYP pin is clamped internally
OUT1
OUT
OUT
–
.
to 0.6V relative to V
. A small capacitor from V
OUT1
OUT
OUT2
to this pin will bypass the reference to lower the output
–
–
V
(Bank 2): V
is the return for both V
and
OUT1
OUT
V
OUT
and V
voltage noise. A maximum value of 0.01µF can be used
–
. V
comprise the isolated output of
OUT2 OUT1
OUT
for reducing output voltage noise to a typical 20µV
RMS
the LTM8048. In most applications, the bulk of the heat
over a 100Hz to 100kHz bandwidth. If not used, this pin
–
flow out of the LTM8048 is through the GND and V
OUT
must be left unconnected.
pads, so the printed circuit design has a large impact on
the thermal performance of the part. See the PCB Layout
RUN (Pin F3): A resistive divider connected to V and this
IN
and Thermal Considerations sections for more details.
pin programs the minimum voltage at which the LTM8048
will operate. Below 1.24V, the LTM8048 does not deliver
power to the secondary. Above 1.24V, power will be de-
livered to the secondary and 10µA will be fed into the SS
pin. When RUN is less than 1.24V, the pin draws 2.5µA,
allowing for a programmable hysteresis. Do not allow a
negative voltage (relative to GND) on this pin.
–
Apply an external capacitor between V
and V
.
OUT1
OUT
V
(Bank 3): The output of the secondary side linear
OUT2
postregulator.Applytheloadandoutputcapacitorbetween
–
V
OUT2
andV
.SeetheApplicationsInformationsection
OUT
for more information on output capacitance and reverse
output characteristics.
ADJ1 (Pins G7): Apply a resistor from this pin to GND to
GND (Bank 4): This is the primary side local ground of the
–
set the output voltage V
relative to V
, using the
OUT1
OUT
LTM8048primary.Inmostapplications,thebulkoftheheat
recommended value given in Table 1. If Table 1 does not
–
flow out of the LTM8048 is through the GND and V
OUT
list the desired V
value, the equation
OUT1
pads, so the printed circuit design has a large impact on
the thermal performance of the part. See the PCB Layout
and Thermal Considerations sections for more details.
–0.879
kΩ
RADJ1 = 28.4 V
OUT1
may be used to approximate the value. To the seasoned
designer,thisexponentialequationmayseemunusual.The
equation is exponential due to non-linear current sources
that are used to temperature compensate the regulation.
V (Bank 5): V supplies current to the LTM8048’s inter-
IN
IN
nal regulator and to the integrated power switch. These
pins must be locally bypassed with an external, low ESR
capacitor.
BIAS (Pin H5): This pin supplies the power necessary to
operate the LTM8048. It must be locally bypassed with a
low ESR capacitor of at least 4.7μF. Do not allow this pin
ADJ2(pinA2):Thisistheinputtotheerroramplifierofthe
secondary side LDO post regulator. This pin is internally
clamped to 7V. The ADJ2 pin voltage is 1.22V referenced
–
voltage to rise above V .
to V
and the output voltage range is 1.22V to 12V. Ap-
IN
OUT
–
ply a resistor from this pin to V
, using the equation
OUT
SS(PinH6):Placeasoft-startcapacitorheretolimitinrush
current and the output voltage ramp rate. Do not allow a
negative voltage (relative to GND) on this pin.
R
= 608.78/(V
– 1.22)kΩ. If the post regulator
ADJ2
OUT2
is not used, leave this pin floating.
8048fg
7
For more information www.linear.com/LTM8048