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LTM2220IV-AA#PBF PDF预览

LTM2220IV-AA#PBF

更新时间: 2024-01-11 09:03:18
品牌 Logo 应用领域
凌特 - Linear 转换器
页数 文件大小 规格书
32页 763K
描述
IC 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PBCC100, 16 X 16 MM, MO-222, SIPLGA-100, Analog to Digital Converter

LTM2220IV-AA#PBF 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:QCCN, LGA100,25X25,20
针数:100Reach Compliance Code:compliant
ECCN代码:3A991.C.2HTS代码:8542.39.00.01
风险等级:5.83最大模拟输入电压:3.5 V
转换器类型:ADC, PROPRIETARY METHODJESD-30 代码:S-PBCC-N100
JESD-609代码:e3长度:16 mm
最大线性误差 (EL):0.0366%湿度敏感等级:3
模拟输入通道数量:1位数:12
功能数量:1端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
输出位码:BINARY, 2'S COMPLEMENT BINARY输出格式:PARALLEL, WORD
封装主体材料:PLASTIC/EPOXY封装代码:QCCN
封装等效代码:LGA100,25X25,20封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):250
电源:3.3 V认证状态:Not Qualified
采样速率:170 MHz采样并保持/跟踪并保持:SAMPLE
座面最大高度:2.13 mm子类别:Analog to Digital Converters
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:16 mm
Base Number Matches:1

LTM2220IV-AA#PBF 数据手册

 浏览型号LTM2220IV-AA#PBF的Datasheet PDF文件第2页浏览型号LTM2220IV-AA#PBF的Datasheet PDF文件第3页浏览型号LTM2220IV-AA#PBF的Datasheet PDF文件第4页浏览型号LTM2220IV-AA#PBF的Datasheet PDF文件第5页浏览型号LTM2220IV-AA#PBF的Datasheet PDF文件第6页浏览型号LTM2220IV-AA#PBF的Datasheet PDF文件第7页 
LTC2220/LTC2221  
12-Bit,170Msps/  
135Msps ADCs  
U
FEATURES  
DESCRIPTIO  
TheLTC®2220andLTC2221are170Msps/135Msps,sam-  
pling 12-bit A/D converters designed for digitizing high  
frequency, wide dynamic range signals. The LTC2220/  
LTC2221 are perfect for demanding communications  
applications with AC performance that includes 67.5dB  
SNR and 80dB spurious free dynamic range for signals  
up to 170MHz. Ultralow jitter of 0.15psRMS allows  
undersampling of IF frequencies with excellent noise  
performance.  
Sample Rate: 170Msps/135Msps  
67.5dB SNR up to 140MHz Input  
80dB SFDR up to 170MHz Input  
775MHz Full Power Bandwidth S/H  
Single 3.3V Supply  
Low Power Dissipation: 890mW/660mW  
LVDS, CMOS, or Demultiplexed CMOS Outputs  
Selectable Input Ranges: ±0.5V or ±1V  
No Missing Codes  
Optional Clock Duty Cycle Stabilizer  
DC specs include ±0.4LSB INL (typ), ±0.3LSB DNL (typ)  
Shutdown and Nap Modes  
and no missing codes over temperature. The transition  
Data Ready Output Clock  
noise is a low 0.5LSBRMS  
.
Pin Compatible Family  
The digital outputs can be either differential LVDS, or  
single-ended CMOS. There are three format options for  
theCMOSoutputs:asinglebusrunningatthefulldatarate  
or two demultiplexed buses running at half data rate with  
either interleaved or simultaneous update. A separate  
output power supply allows the CMOS output swing to  
range from 0.5V to 3.6V.  
The ENC+ and ENCinputs may be driven differentially or  
singleendedwithasinewave, PECL, LVDS, TTL, orCMOS  
inputs. An optional clock duty cycle stabilizer allows high  
performance at full speed for a wide range of clock duty  
cycles.  
185Msps: LTC2220-1 (12-Bit)  
170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)  
135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)  
64-Pin 9mm × 9mm QFN Package  
U
APPLICATIO S  
Wireless and Wired Broadband Communication  
Cable Head-End Systems  
Power Amplifier Linearization  
Communications Test Equipment  
, LTC and LT are registered trademarks of Linear Technology Corporation.  
All other trademarks are the property of their respective owners.  
U
TYPICAL APPLICATIO  
SFDR vs Input Frequency  
3.3V  
V
DD  
100  
90  
0.5V  
TO 3.6V  
REFH  
REFL  
FLEXIBLE  
REFERENCE  
OV  
DD  
4th OR HIGHER  
80  
70  
60  
50  
40  
D11  
+
12-BIT  
PIPELINED  
ADC CORE  
CMOS  
OR  
CORRECTION  
LOGIC  
ANALOG  
INPUT  
OUTPUT  
DRIVERS  
INPUT  
S/H  
LVDS  
D0  
2nd OR 3rd  
OGND  
CLOCK/DUTY  
CYCLE  
CONTROL  
22201 TA01  
200  
300  
0
100  
400  
500  
600  
ENCODE  
INPUT  
INPUT FREQUENCY (MHz)  
22201 TA01b  
22201fa  
1

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