LTC6905
W U U
U
APPLICATIO S I FOR ATIO
SELECTING THE DIVIDER SETTING AND RESISTOR
Example:AnLTC6905isoperatingwitha3Vpowersupply
and is set for a fOSC = 50MHz.
ROUT with V+ = 3V is 27Ω (using the ROUT vs V+ graph in
the Typical Performance Characteristics).
The LTC6905’s master oscillator has a frequency range
spanning 68.9MHz to 170MHz. A programmable divider
extendsthefrequencyrangefrom17.225MHzto170MHz.
Table 1 describes the recommended frequencies for each
divider setting. Note that the ranges overlap; at some
frequencies there are two divider/resistor combinations
that result in the same frequency. Choosing a higher
divider setting will result in less jitter at the expense of
slightly higher supply current.
The maximum output CLOAD should be equal to or less
than [45454/(27 • 50)] = 33.6pF.
The lowest resistive load Pin 5 can drive can be calculated
using the minimum high level output voltage in the Elec-
trical Characteristics. With a V+ equal to 5.5V and 4mA
output current, the minimum high level output voltage is
5V and the lowest resistive load Pin 5 can drive is 1.25k
(5V/4mA). With a V+ equal to 2.7V and 4mA output
current,theminimumhighleveloutputvoltageis1.9Vand
thelowestresistiveloadPin5candriveis475Ω(1.9V/4mA).
Table 1. Frequency Range vs Divider Setting
DIVIDER SETTING
FREQUENCY RANGE
68.9MHz to 170MHz
34.45MHz to 85MHz
17.225MHz to 43MHz
+
÷1
÷2
÷4
⇒
⇒
⇒
DIV (Pin 4) = V
DIV (Pin 4) = Floating
DIV (Pin 4) = GND
After choosing the proper divider setting, determine the
correct frequency-setting resistor. Because of the linear
correspondence between oscillation period and resis-
tance,asimpleequationrelatesresistancewithfrequency.
FREQUENCY ACCURACY AND POWER SUPPLY NOISE
The frequency accuracy of the LTC6905 may be affected
when its power supply generates noise with frequency
contentsequaltofMO/64oritsmultiples(fMOistheinternal
LTC6905 master oscillator frequency before the divider
and fMO/64 is the master oscillator control loop fre-
quency). If for example, the master oscillator frequency is
set equal to 80MHz and the LTC6905 is powered by a
switching regulator, then the oscillator frequency may
show an additional error if the switching frequency is
1.4MHz (80MHz/64).
1
⎧
10k ⎛ 168.5MHz ⎞
N
⎪
RSET
=
•
, N = 2
⎨
⎟
⎜
⎝ fOSC – 1.5MHz⎠
(RSETMIN = 10k, RSETMAX = 25k)
Any resistor, RSET, tolerance adds to the inaccuracy of the
⎪4
⎩
oscillator, fOSC
.
START-UP TIME
JITTER AND POWER SUPPLY NOISE
Thestart-uptimeandsettlingtimetowithin1%ofthefinal
frequency is typically 100µs.
If the LTC6905 is powered by a supply that has frequency
contentsequaltotheoutputfrequencythentheoscillators
jitter may increase. In addition, power supply ripple in
excess of 20mV at any frequency may increase jitter.
MAXIMUM OUTPUT LOAD
The LTC6905 output (Pin 5) can drive a capacitive load
(CLOAD) of 5pF or more. Driving a CLOAD greater than 5pF
depends on the oscillator’s frequency (fOSC) and output
resistance (ROUT). The output rise time or fall time due to
ROUT and CLOAD is equal to 2.2 • ROUT • CLOAD (from 10%
to 90% of the rise or fall transition). If the total output rise
time plus fall time is arbitrarily specified to be equal to or
less than 20% of the oscillator’s period (1/fOSC), then the
maximumoutputCLOADinpicofarads(pF)shouldbeequal
to or less than [45454/(ROUT • fOSC)] (ROUT in ohms and
fOSC in MHz).
JITTER AND DIVIDE RATIO
At a given output frequency, a higher master oscillator
frequency and a higher divide ratio will result in lower jitter
and higher power supply dissipation. Indeterminate jitter
percentage will decrease by a factor of slightly less than
the square root of the divider ratio, while determinate jitter
will not be similarly attenuated. Please consult the speci-
ficationtablesandJittervsFrequencygraphshowingjitter
at various divider ratios.
6905fa
6